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1 hd66724/hd66725 (graphics lcd controller/driver with key scan function) ade-207-309(z) rev 1.2 '99.8 description the hd66724/hd66725, dot-matrix graphics lcd controller and driver lsi incorporating a key scan function up to a 4-by-8 key matrix, display characters such as alphanumerics, katakana, hiragana and symbols as well as graphics such as kanji and pictograms. they can be configured to drive a dot-matrix liquid crystal display and control key scan functions under the control of the microprocessor connected via the clock-synchronized serial or 4/8-bit bus. the hd66724 is capable of displaying up to three 12- character lines, 72-by-24 dot graphics and 144 segments. the hd66725 is capable of displaying up to three 16-character lines, 96-by-24 dot graphics and 192 segments. of the 144 (192) segments displayed, 48 (64) segments can be grayscaled. the hd66724/hd66725 have a smooth horizontal/vertical scroll display and double-height display so that the user can easily see a variety of information within a small lcm. the hd66724/hd66725 have various functions to reduce the power consumption of an lcd system such as low-voltage operation of 1.8 v or less, a booster to generate maximum triple lcd drive voltage from the supplied voltage, and voltage-followers to decrease the direct current flow in the lcd drive bleeder- resistors. combining these hardware functions with software functions such as standby and sleep modes allows fine power control. the hd66724/hd66725 are suitable for any portable battery-driven product requiring long-term driving capabilities and small physical dimensions such as cellular phones, pagers, portable audio devices, or electronic wallets. features control and drive of a character and graphics lcd with built-in key scan functions three 12- (16-) character lines, 72 (96) -by-24 dot graphics, and 144 (192) segments 48 (64) grayscale segments control up to a 4 8 (32 key) matrix key scan. 3 general ports built-in low-power operation support:
hd66724/hd66725 2 ? vcc = 1.8 to 5.5 v (low voltage) ? v lcd = 3.0 to 6.5 v (liquid crystal drive voltage) ? single, double or triple booster for liquid crystal drive voltage ? contrast adjuster and voltage followers to decrease direct current flow in the lcd drive bleeder- resistors ? wake-up feature using key scan interrupt ? programmable drive duty ratios and bias values displayed on lcd clock-synchronized serial interface 4-/8-bit bus interface capability (except when key scan circuit is used) 80 8-bit display data ram (80 characters max) 20,736-bit (6 8 dots : 432 characters) character generator rom 384 8-bit (64 characters) character generator ram 96 2-bit (192 segment-icons and marks max) segment ram 72- (96-) segment 26-common-signal liquid crystal display driver programmable display sizes and duty ratios vertical and horizontal smooth scrolls vertical double-height display selectable cgrom memory bank (max. 432 fonts) wide range of instruction functions: ? clear display, display on/off control, icon and mark control, character blink, black-white reversed blinking cursor, return home, cursor on/off, black-white reversed raster-row no wait time for instruction execution and ram access (zero instruction) internal oscillation (with external or built-in resistor) hardware reset shift change of segment and common driver slim chip with bumps for chip-on-glass (cog) mounting, and tape carrier package (tcp) table 1 progammable display sizes and duty ratios character display graphics display duty ratio optimum drive bias hd66724 hd66725 hd66724 hd66725 segment display scanned keys general ports 1/2 1/2 unavailable unavailable unavailable unavailable 32 (4 x 8) 3 1/10 1/4 1 line x 12 characters 1 line x 16 characters 72 x 8 dots 96 x 8 dots hd66724: 144 1/18 1/5 2 lines x 12 characters 2 lines x 16 characters 72 x 16 dots 96 x 16 dots hd66725: 192 1/26 1/6 3 lines x 12 characters 3 lines x 16 characters 72 x 24 dots 96 x 24 dots
hd66724/hd66725 3 total current consumption characteristics (vcc = 3 v, fosc = 32 khz, typ conditions, lcd drive power current included) total power consumption normal display operation character display size duty ratio optimum drive bias frame frequency internal logic lcd power total* sleep mode standby mode segment only 1/2 1/2 80 hz (14 m a) (12 m a) (26 m a) (11 m a) 0.1 m a 1-line display 1/10 1/4 80 hz (20 m a) (17 m a) (54 m a) (11 m a) 2-line display 1/18 1/5 74 hz (20 m a) (17 m a) (54 m a) (11 m a) 3-line display 1/26 1/6 77 hz (20 m a) (17 m a) (54 m a) (11 m a) note : when duty ratio = 1/2 and a double booster is not used: the total power consumption = internal logic current + lcd power current when duty ratio = 1/10 and a double booster is used: the total power consumption = internal logic current + lcd power current x 2 type name types external dimensions operation voltages internal fonts hd66724ra03ta0l tcp 1.8 v to 5.5 v katakana, alphanumerics, symbols hcd66724ra03bp au-bumped chip and european fonts HD66725A03TA0L tcp hcd66725a03bp au-bumped chip
hd66724/hd66725 4 lcd-ii family comparison items hd66712u hd66720 hd66705u character display sizes 12 characters x 4 lines 8 characters x 2 lines 12 characters x 2 lines graphic display sizes multiplexing icons 60 42 40 annunciator static: 10 key scan control 5 x 6 led control ports 2 general output port operating power voltages 2.7 v to 5.5 v 2.7 v to 5.5 v 2.4 v to 5.5 v liquid crystal drive voltages 3 v to 13 v 3 v to 11 v 3 v to 9 v serial bus clock-synchronized serial clock-synchronized serial clock-synchronized serial parallel bus 4 bits, 8 bits 4 bits, 8 bits expansion driver control possible possible impossible liquid crystal drive duty ratios 1/17, 33 1/9, 17 1/10, 18 liquid crystal drive biases 1/4 to 1/6, 7 1/4 to 1/5 1/4 liquid crystal drive waveforms b b b liquid crystal voltage booster double or triple double or triple double or triple bleeder-resistor for liquid crystal drive external external incorporated (external) liquid crystal drive operational amplifier incorporated liquid crystal contrast adjuster incorporated horizontal smooth scroll dot unit dot unit vertical smooth scroll line unit double-height display yes ddram 80 x 8 40 x 8 60 x 8 cgrom 9,600 9,600 9,600 cgram 64 x 8 64 x 8 32 x 5 segram 16 x 8 16 x 8 8 x 5 no. of cgrom fonts 240 240 240 no. of cgram fonts 8 8 4 font sizes 5 x 8 5 x 8 5 x 8 bit map area r-c oscillation resistor/oscillation frequency external resistor (270 khz) external resistor (150 khz) external resistor (40, 80 khz) reset function incorporated, external incorporated, external external low power control lp display mode lp display mode simple standby partial display off display off oscillation off liquid crystal power off seg/com direction switching seg only qfp package (s mask) qfp-1420 tqfp package tqfp-1414 tcp package tcp-128 tcp-153 bare chip yes yes yes bumped chip yes yes no. of pins 128 100 153 chip sizes 4.95 x 5.27 5.60 x 6.00 9.69 x 2.73 pad intervals 128 m m 160 m m 120 m m
hd66724/hd66725 5 lcd-ii family comparison (cont) items hd66717 hd66727 hd66724 character display sizes 12 characters x 4 lines 12 characters x 4 lines 12 characters x 3 lines graphic display sizes 72 x 26 dots multiplexing icons 40 40 144 annunciator static: 10 static: 12 1/2 duty: 144 key scan control 4 x 8 8 x 4 led control ports 3 general output ports 3 3 operating power voltages 2.4 v to 5.5 v 2.4 v to 5.5 v 1.8 v to 5.5 v liquid crystal drive voltages 3 v to 13 v 3 v to 13 v 3 v to 6 v serial bus i2c, clock-synchronized serial i2c, clock-synchronized serial clock-synchronized serial parallel bus 4 bits, 8 bits 4 bits, 8 bits expansion driver control impossible impossible impossible liquid crystal drive duty ratios 1/10, 18, 26, 34 1/10, 18, 26, 34 1/2, 10, 18, 26 liquid crystal drive biases 1/4, 1/6 1/4, 1/6 1/4 to 1/6.5 liquid crystal drive waveforms b b b liquid crystal voltage booster double or triple double or triple single, double or triple bleeder-resistor for liquid crystal drive incorporated (external) incorporated (external) incorporated (external) liquid crystal drive operational amplifier incorporated incorporated incorporated liquid crystal contrast adjuster incorporated incorporated incorporated horizontal smooth scroll 3-dot unit vertical smooth scroll line unit line unit line unit double-height display yes yes yes ddram 60 x 8 60 x 8 80 x 8 cgrom 9,600 11,520 20,736 cgram 32 x 5 32 x 6 384 x 8 segram 8 x 5 8 x 6 72 x 8 no. of cgrom fonts 240 240 240 + 192 no. of cgram fonts 4 4 64 font sizes 5 x 8 5 x 8, 6 x 8 6 x 8 bit map area 72 x 26 r-c oscillation resistor/ oscillation frequency external resistor (40-160 khz) external resistor (40-160 khz) external resistor, incorporated (32 khz) reset function external external external low power control partial display off display off oscillation off liquid crystal power off partial display off display off oscillation off liquid crystal power off key wake-up interrupt partial display off display off oscillation off liquid crystal power off key wake-up interrupt seg/com direction switching seg only seg, com seg, com qfp package tqfp package tcp package tcp-153 tcp-158 tcp-146 bare chip yes yes bumped chip yes yes yes no. of pins 153 158 146 chip sizes 10.88 x 2.89 11.39 x 2.89 10.34 x 2.51 pad intervals 120 m m 120 m m 80 m m
hd66724/hd66725 6 lcd-ii family comparison (cont) items hd66725 hd66726 hd66730 character display sizes 16 characters x 3 lines 16 characters x 5 lines 6 (12) characters x 2 lines graphic display sizes 96 x 26 dots 96 x 42 dots multiplexing icons 192 192 71 annunciator 1/2 duty: 192 1/2 duty: 192 key scan control 8 x 4 8 x 4 led control ports general output ports 3 3 operating power voltages 1.8 v to 5.5 v 1.8 v to 5.5 v 2.4 v to 5.5 v liquid crystal drive voltages 3 v to 6 v 4.0 v to 13 v 3 v to 15 v serial bus clock-synchronized serial clock-synchronized serial clock-synchronized serial parallel bus 4 bits, 8 bits 4 bits, 8 bits 8 bits expansion driver control impossible impossible possible liquid crystal drive duty ratios 1/2, 10, 18, 26 1/2, 10, 18, 26, 34, 42 1/14, 27, 40, 53 liquid crystal drive biases 1/4 to 1/6.5 1/2 to 1/8 1/4 to 1/8.3 liquid crystal drive waveforms b b b liquid crystal voltage booster single, double, or triple single, double, triple, or quadruple double or triple bleeder-resistor for liquid crystal drive incorporated (external) incorporated (external) external liquid crystal drive operational amplifier incorporated incorporated liquid crystal contrast adjuster incorporated incorporated horizontal smooth scroll 3-dot unit 3-dot unit display unit vertical smooth scroll line unit line unit line unit double-height display yes yes ddram 80 x 8 80 x 8 80 x 8 cgrom 20,736 20,736 506,880 + 9,216 cgram 384 x 8 480 x 8 32 x 6 segram 96 x 8 96 x 8 8 x 6 no. of cgrom fonts 240 + 192 240 + 192 3,840 no. of cgram fonts 64 64 8 font sizes 6 x 8 6 x 8 11 x 12 bit map areas 96 x 26 96 x 42 r-c oscillation resistor/ oscillation frequency external resistor, incorporated (32 khz) external resistor (50 khz) external resistor (70?50 khz) reset function external external external low power control partial display off display off oscillation off liquid crystal power off key wake-up interrupt partial display off display off oscillation off liquid crystal power off key wake-up interrupt booster off internal division function seg/com direction switching seg, com seg, com qfp package qfp-1420 tqfp package tcp package tcp-170 tcp-188 bare chip yes bumped chip yes yes no. of pins 170 188 128 chip sizes 10.97 x 2.51 13.13 x 2.51 7.48 x 6.46 pad intervals 80 m m 80 m m 180 m m
hd66724/hd66725 7 lcd-ii family comparison (cont) items hd66731 character display sizes 10 (20) characters x 4 lines graphic display sizes multiplexing icons 120 annunciator key scan control led control ports general output ports operating power voltages 2.4 v to 5.5 v liquid crystal drive voltages 3 v to 15 v serial bus clock-synchronized serial parallel bus 8 bits expansion driver control possible liquid crystal drive duty ratios 1/14, 27, 40, 53 liquid crystal drive biases 1/4 to 1/8.3 liquid crystal drive waveforms b liquid crystal voltage booster double or triple bleeder-resistor for liquid crystal drive external liquid crystal drive operational amplifier liquid crystal contrast adjuster horizontal smooth scroll display unit vertical smooth scroll line unit double-height display ddram 80 x 8 cgrom 506,880 + 9,216 cgram 32 x 6 segram 8 x 6 no. of cgrom fonts 3,840 no. of cgram fonts 8 font sizes 11 x 12 bit map areas r-c oscillation resistor/ oscillation frequency external resistor (70?50 khz) reset function external low power control booster off internal division function seg/com direction switching qfp package tqfp package tcp package tcp-170, 206 bare chip bumped chip yes no. of pins 206 chip sizes 7.48 x 6.46 pad intervals 80 m m
hd66724/hd66725 8 hd66724/hd66725 block diagram system interface ?clock synchro- nized serial ?4-bit bus ?8-bit bus data register (dr) instruction register (ir) address counter (ac) timing generator display data ram (ddram) 80 bytes character generator ram (cgram) 384 bytes character generator rom (cgrom) 20,736 bits parallel/serial converter latch circuit segment shift register segment driver lcd drive voltage selector cursor and blink controller cpg instruction decoder cs* rw/rd*/sda rs e/wr*/scl vcc com1/24 com24/1 seg1/72 (96) seg72 (96)/1 osc1 r1-r3 osc2 8 8 6 10 8 7 7 8 8 6 6 vci double/triple booster c1+ 8 7 segmemt ram (sgram) 24 bytes im2? reset* c1 c2+ c2 vlout +- +- +- +- +- gnd coms1/2, coms2/1 vr rrr 0 r v lcd r test v1out v2out v3out v4out v5out opoff im0/id key scan timing controller key scan registers (scan0?can3) db0/kin0 db7/kin7 kst0 kst3 8 common driver 26-bit bidirectional common shift register general output port port0 port2
hd66724/hd66725 9 hd66724 pad arrangement ?chip size: 10.34 x 2.51 mm ?pad coordinate: pad center ?coordinate origin: chip center ?au bump size: 50 m x 100 m ?au bump pitch: 80 m (min.) top view hd66724 seg16/57 seg15/58 seg14/59 seg13/60 seg12/61 seg11/62 seg10/63 seg9/64 seg8/65 seg7/66 seg6/67 seg5/68 seg4/69 seg3/70 seg2/71 seg26/47 seg25/48 seg24/49 seg23/50 seg22/51 seg21/52 seg20/53 seg19/54 seg18/55 seg36/37 seg35/38 seg34/39 seg33/40 seg32/41 seg31/42 seg30/43 seg29/44 seg28/45 seg27/46 seg42/31 seg41/32 seg40/33 seg39/34 seg38/35 seg37/36 seg43/30 seg17/56 seg1/72 seg44/29 seg45/28 seg46/27 seg47/26 seg48/25 seg49/24 seg50/23 seg51/22 seg52/21 seg53/20 seg54/19 seg55/18 seg56/17 seg57/16 seg58/15 seg59/14 seg60/13 coms1/s2 com1/24 com2/23 com3/22 com4/21 com5/20 com6/19 com8/17 osc2 osc1 vcc com7/18 vci dummy41 dummy31 c1+ y x com20/5 com19/6 com18/7 seg61/12 seg62/11 seg63/10 seg64/9 seg65/8 seg66/7 seg67/6 seg68/5 seg69/4 seg70/3 seg71/2 seg72/1 c1+ c1+ c2- c2- c2+ c2+ vci vci vcc vcc gnd gnd gnd db0/kin0 db1/kin1 db2/kin2 db3/kin3 db4/kin4 db5/kin5 db6/kin6 db7/kin7 kst0 kst1 kst2 kst3 irq* r1 r2 r3 com17/8 rw/rd*/sda e/wr*/scl cs* reset* port0 port1 c1- c1- c1- com9/16 com10/15 com11/14 com12/13 com13/12 com14/11 com15/10 com16/9 dummy32 dummy33 dummy34 dummy36 dummy37 dummy38 dummy39 dummy40 dummy42 dummy43 coms2/s1 com24/1 com23/2 com22/3 com21/4 dummy47 dummy48 dummy44 vtest3 vtest2 vtest1 v5out v5out v4out v4out v3out v3out v2out v2out v1out v1out dummy22 dummy3 dummy4 dummy11 dummy12 dummy2 dummy13 c1- c1- vlout vlout vlout vlout v lcd v lcd v lcd v lcd c2- c2- c1+ c1+ c2+ c2+ vci vci vcc vcc port2 dummy16 dummy15 rs rw/rd*/sda gnd dummy17 dummy35 dummy30 dummy29 dummy28 dummy27 dummy26 dummy25 dummy24 dummy23 dummy45 dummy46 dummy49 dummy50 dummy51 dummy52 dummy53 dummy54 dummy55 dummy56 dummy57 dummy58 dummy59 dummy1 vcc gnd gnd gnd gnd e/wr*/scl rs cs* reset* db0/kin0 db1/kin1 db2/kin2 db3/kin3 db4/kin4 db5/kin5 db6/kin6 db7/kin7 kst0 kst1 kst2 kst3 irq* port0 port1 port2 gnddum im2 im1 im0/id vccdum opoff test dummy8 dummy9 dummy10 dummy5 dummy6 dummy7 dummy14 dummy18 dummy19 dummy20 dummy21 2
hd66724/hd66725 10 hd66724 pad coordinates no. pad name x y no. pad name x y no. pad name x y no. pad name x y no. pad name x y dummy15 ?994 ?079 50 gnd 564 ?079 104 v3out 4915 ?69 142 seg18/55 1572 999 dummy41 ?863 999 dummy16 ?771 ?079 51 gnd 644 ?079 105 v3out 4915 ?89 143 seg19/54 1492 999 dummy42 ?943 999 dummy17 ?690 ?079 52 gnd 725 ?079 106 v4out 4915 ?08 144 seg20/53 1411 999 dummy43 ?024 999 dummy18 ?610 ?079 53 gnd 806 ?079 107 v4out 4915 ?27 145 seg21/52 1331 999 dummy44 ?105 999 dummy19 ?529 ?079 54 gnd 886 ?079 108 v5out 4915 ?47 146 seg22/51 1250 999 dummy45 ?185 999 dummy20 ?449 ?079 55 gnd 967 ?079 109 v5out 4915 ?6 147 seg23/50 1169 999 dummy46 ?266 999 dummy21 ?368 ?079 56 gnd 1048 ?079 110 vtest1 4915 15 148 seg24/49 1089 999 197 coms2/s1 ?347 999 1 gnddum ?207 ?079 57 gnd 1128 ?079 111 vtest2 4915 95 149 seg25/48 1008 999 198 com24/1 ?427 999 2 im2 ?126 ?079 58 osc2 1209 ?079 112 vtest3 4915 176 150 seg26/47 927 999 199 com23/2 ?508 999 3 im1 ?942 ?079 59 r3 1364 ?94 113 com9/16 4915 282 151 seg27/46 847 999 200 com22/3 ?588 999 4 im0/id ?758 ?079 60 r2 1445 ?94 114 com10/15 4915 363 152 seg28/45 766 999 201 com21/4 ?669 999 5 vccdum ?655 ?079 61 r1 1525 ?94 115 com11/14 4915 444 153 seg29/44 685 999 dummy47 ?830 1079 6 opoff ?574 ?079 62 osc1 1680 ?079 116 com12/13 4915 524 154 seg30/43 605 999 dummy48 ?911 1079 7 test ?390 ?079 63 vcc 1783 ?079 117 com13/12 4915 605 155 seg31/42 524 999 dummy49 ?992 1079 8 port2 ?287 ?079 64 vcc 1864 ?079 118 com14/11 4915 685 156 seg32/41 444 999 dummy50 ?072 1079 9 port2 ?206 ?079 65 vcc 1945 ?079 119 com15/10 4915 766 157 seg33/40 363 999 dummy51 ?153 1079 10 port1 ?103 ?079 66 vcc 2025 ?079 120 com16/9 4915 847 158 seg34/39 282 999 dummy52 ?234 1079 11 port1 ?022 ?079 67 vcc 2106 ?079 dummy23 4915 1079 159 seg35/38 202 999 dummy53 ?314 1079 12 port0 ?919 ?079 68 vcc 2187 ?079 dummy24 4717 1079 160 seg36/37 121 999 dummy54 ?395 1079 13 port0 ?838 ?079 69 vci 2290 ?99 dummy25 4637 1079 161 seg37/36 40 999 dummy55 ?476 1079 14 irq* ?735 ?079 70 vci 2371 ?99 dummy26 4556 1079 162 seg38/35 ?0 999 dummy56 ?556 1079 15 irq* ?654 ?079 71 vci 2451 ?99 dummy27 4476 1079 163 seg39/34 ?21 999 dummy57 ?637 1079 16 kst3 ?551 ?079 72 vci 2532 ?99 dummy28 4395 1079 164 seg40/33 ?02 999 dummy58 ?717 1079 17 kst3 ?470 ?079 73 vci 2613 ?99 dummy29 4314 1079 165 seg41/32 ?82 999 dummy59 ?798 1079 18 kst2 ?367 ?079 74 c2+ 2693 ?99 dummy30 4234 1079 166 seg42/31 ?63 999 dummy1 ?994 1079 19 kst2 ?286 ?079 75 c2+ 2774 ?99 dummy31 4153 1079 167 seg43/30 ?44 999 202 com8/17 ?915 847 20 kst1 ?183 ?079 76 c2+ 2854 ?99 dummy32 4072 1079 168 seg44/29 ?24 999 203 com7/18 ?915 766 21 kst1 ?102 ?079 77 c2+ 2935 ?99 dummy33 3992 1079 169 seg45/28 ?05 999 204 com6/19 ?915 685 22 kst0 ?999 ?079 78 c2 3016 ?99 dummy34 3911 1079 170 seg46/27 ?85 999 205 com5/20 ?915 605 23 kst0 ?918 ?079 79 c2 3096 ?99 121 com17/8 3750 999 171 seg47/26 ?66 999 206 com4/21 ?915 524 24 db7/kin7 ?815 ?079 80 c2 3177 ?99 122 com18/7 3669 999 172 seg48/25 ?47 999 207 com3/22 ?915 444 25 db7/kin7 ?734 ?079 81 c2 3258 ?99 123 com19/6 3588 999 173 seg49/24 ?27 999 208 com2/23 ?915 363 26 db6/kin6 ?631 ?079 82 c1+ 3338 ?99 124 com20/5 3508 999 174 seg50/23 ?008 999 209 com1/24 ?915 282 27 db6/kin6 ?551 ?079 83 c1+ 3419 ?99 dummy35 3427 999 175 seg51/22 ?089 999 210 coms1/s2 ?915 202 28 db5/kin5 ?447 ?079 84 c1+ 3500 ?99 dummy36 3347 999 176 seg52/21 ?169 999 dummy2 ?994 50 29 db5/kin5 ?367 ?079 85 c1+ 3580 ?99 dummy37 3266 999 177 seg53/20 ?250 999 dummy3 ?994 ?0 30 db4/kin4 ?263 ?079 86 c1+ 3661 ?99 dummy38 3185 999 178 seg54/19 ?331 999 dummy4 ?994 ?11 31 db4/kin4 ?183 ?079 87 c1 3741 ?99 dummy39 3105 999 179 seg55/18 ?411 999 dummy5 ?994 ?92 32 db3/kin3 ?079 ?079 88 c1 3822 ?99 dummy40 3024 999 180 seg56/17 ?492 999 dummy6 ?994 ?72 33 db3/kin3 ?99 ?079 89 c1 3903 ?99 125 seg1/72 2943 999 181 seg57/16 ?572 999 dummy7 ?994 ?53 34 db2/kin2 ?95 ?079 90 c1 3983 ?99 126 seg2/71 2863 999 182 seg58/15 ?653 999 dummy8 ?994 ?33 35 db2/kin2 ?15 ?079 91 c1 4064 ?99 127 seg3/70 2782 999 183 seg59/14 ?734 999 dummy9 ?994 ?14 36 db1/kin1 ?11 ?079 92 vlout 4145 ?99 128 seg4/69 2701 999 184 seg60/13 ?814 999 dummy10 ?994 ?95 37 db1/kin1 ?31 ?079 93 vlout 4225 ?99 129 seg5/68 2621 999 185 seg61/12 ?895 999 dummy11 ?994 ?75 38 db0/kin0 ?27 ?079 94 vlout 4306 ?99 130 seg6/67 2540 999 186 seg62/11 ?976 999 dummy12 ?994 ?56 39 db0/kin0 ?47 ?079 95 vlout 4387 ?99 131 seg7/66 2460 999 187 seg63/10 ?056 999 dummy13 ?994 ?37 40 reset* ?43 ?079 96 vlcd 4467 ?99 132 seg8/65 2379 999 188 seg64/9 ?137 999 dummy14 ?994 ?17 41 reset* ?63 ?079 97 vlcd 4548 ?99 133 seg9/64 2298 999 189 seg65/8 ?218 999 42 cs* ?59 ?079 98 vlcd 4629 ?99 134 seg10/63 2218 999 190 seg66/7 ?298 999 43 cs* ?9 ?079 99 vlcd 4709 ?99 135 seg11/62 2137 999 191 seg67/6 ?379 999 44 rs 24 ?079 dummy22 4915 ?079 136 seg12/61 2056 999 192 seg68/5 ?460 999 45 rs 105 ?079 100 v1out 4915 ?92 137 seg13/60 1976 999 193 seg69/4 ?540 999 46 e/wr*/scl 198 ?079 101 v1out 4915 ?11 138 seg14/59 1895 999 194 seg70/3 ?621 999 47 e/wr*/scl 279 ?079 102 v2out 4915 ?31 139 seg15/58 1814 999 195 seg71/2 ?701 999 48 rw/rd*/sda 368 ?079 103 v2out 4915 ?50 140 seg16/57 1734 999 196 seg72/1 ?782 999 49 rw/rd*/sda 449 ?079 141 seg17/56 1653 999
hd66724/hd66725 11 hd66725 pad arrangement ?chip size: 10.97 x 2.51 mm ?pad coordinates: pad center ?coordinate origin: chip center ?au bump size: 50 m x 100 m ?au bump pitch: 80 m (min.) (top view) hd66725 seg16/81 seg15/82 seg14/83 seg13/84 seg12/85 seg11/86 seg10/87 seg9/64 seg8/89 seg7/90 seg6/91 seg5/92 seg4/93 seg3/94 seg2/95 seg26/71 seg25/72 seg24/73 seg23/74 seg22/75 seg21/76 seg20/77 seg19/78 seg18/79 seg36/61 seg35/62 seg34/63 seg33/64 seg32/65 seg31/66 seg30/67 seg29/68 seg28/69 seg27/70 seg42/55 seg41/56 seg40/57 seg39/58 seg38/59 seg37/60 seg43/54 seg17/80 seg1/96 seg44/53 seg45/52 seg46/51 seg47/50 seg48/49 seg49/48 seg50/47 seg51/46 seg52/45 seg53/44 seg54/43 seg55/42 seg56/41 seg57/40 seg58/39 seg59/38 seg60/37 coms1/s2 com1/24 com2/23 com3/22 com4/21 com5/20 com6/19 com8/17 osc2 osc1 vcc com7/18 vci dummy37 c1+ y x com20/5 com19/6 com18/7 seg61/36 seg62/35 seg63/34 seg64/33 seg65/32 seg66/31 seg67/30 seg68/29 seg69/28 seg70/27 seg71/26 seg72/25 c1+ c1+ c2- c2- c2+ c2+ vci vci vcc vcc gnd gnd gnd db0/kin0 db1/kin1 db2/kin2 db3/kin3 db4/kin4 db5/kin5 db6/kin6 db7/kin7 kst0 kst1 kst2 kst3 irq* r1 r2 r3 com17/8 rw/rd*/sda e/wr*/scl cs* reset* port0 port1 c1- c1- c1- com9/16 com10/15 com11/14 com12/13 com13/12 com14/11 com15/10 com16/9 dummy38 dummy39 dummy40 dummy44 dummy45 vtest3 vtest2 vtest1 v5out v5out v4out v4out v3out v3out v2out v2out v1out v1out dummy25 dummy2 c1- c1- vlout vlout vlout vlout v lcd v lcd v lcd v lcd c2- c2- c1+ c1+ c2+ c2+ vci vci vcc vcc port2 dummy17 dummy10 rs rw/rd*/sda gnd dummy18 dummy43 dummy36 dummy35 dummy34 dummy33 dummy32 dummy31 dummy30 dummy29 dummy46 dummy47 dummy48 dummy49 dummy50 dummy51 dummy52 dummy53 dummy1 vcc gnd gnd gnd gnd e/wr*/scl rs cs* reset* db0/kin0 db1/kin1 db2/kin2 db3/kin3 db4/kin4 db5/kin5 db6/kin6 db7/kin7 kst0 kst1 kst2 kst3 irq* port0 port1 port2 gnddum im2 im1 im0/id vccdum opoff test dummy6 dummy7 dummy8 dummy3 dummy4 dummy5 dummy19 dummy20 dummy21 dummy22 seg73/24 seg74/23 seg75/22 seg76/21 seg77/20 seg78/19 seg79/18 seg80/17 seg81/16 seg82/15 seg83/14 seg84/13 seg85/12 seg86/11 seg87/10 seg88/9 seg89/8 seg90/7 seg91/6 seg92/5 seg93/4 seg94/3 seg95/2 seg96/1 com21/4 com22/3 com23/2 com24/1 coms2/s1 dummy16 dummy15 dummy14 dummy13 dummy9 dummy12 dummy11 dummy54 dummy23 dummy24 dummy27 dummy26 dummy28 dummy42 dummy41 2
hd66724/hd66725 12 hd66725 pad coordinates no. pad name x y no. pad name x y no. pad name x y no. pad name x y no. pad name x y dummy10 ?309 ?079 46 e/wr*/scl 513 ?079 103 v2out 5230 ?50 146 seg22/75 1726 999 206 seg82/15 ?112 999 dummy11 ?101 ?079 47 e/wr*/scl 594 ?079 104 v3out 5230 ?69 147 seg23/74 1646 999 207 seg83/14 ?193 999 dummy12 ?021 ?079 48 rw/rd*/sda 683 ?079 105 v3out 5230 ?89 148 seg24/73 1565 999 208 seg84/13 ?273 999 dummy13 ?940 ?079 49 rw/rd*/sda 764 ?079 106 v4out 5230 ?08 149 seg25/72 1484 999 209 seg85/12 ?354 999 dummy14 ?859 ?079 50 gnd 879 ?079 107 v4out 5230 ?27 150 seg26/71 1404 999 210 seg86/11 ?435 999 dummy15 ?779 ?079 51 gnd 959 ?079 108 v5out 5230 ?47 151 seg27/70 1323 999 211 seg87/10 ?515 999 dummy16 ?698 ?079 52 gnd 1040 ?079 109 v5out 5230 ?6 152 seg28/69 1242 999 212 seg88/9 ?596 999 dummy17 ?617 ?079 53 gnd 1121 ?079 110 vtest1 5230 15 153 seg29/68 1162 999 213 seg89/8 ?677 999 dummy18 ?537 ?079 54 gnd 1201 ?079 111 vtest2 5230 95 154 seg30/67 1081 999 214 seg90/7 ?757 999 dummy19 ?456 ?079 55 gnd 1282 ?079 112 vtest3 5230 176 155 seg31/66 1000 999 215 seg91/6 ?838 999 dummy20 ?375 ?079 56 gnd 1363 ?079 113 com9/16 5230 282 156 seg32/65 920 999 216 seg92/5 ?919 999 dummy21 ?295 ?079 57 gnd 1443 ?079 114 com10/15 5230 363 157 seg33/64 839 999 217 seg93/4 ?999 999 dummy22 ?214 ?079 58 osc2 1524 ?079 115 com11/14 5230 444 158 seg34/63 759 999 218 seg94/3 ?080 999 dummy23 ?134 ?079 59 r3 1679 ?94 116 com12/13 5230 524 159 seg35/62 678 999 219 seg95/2 ?161 999 dummy24 ?053 ?079 60 r2 1760 ?94 117 com13/12 5230 605 160 seg36/61 597 999 220 seg96/1 ?241 999 1 gnddum ?892 ?079 61 r1 1840 ?94 118 com14/11 5230 685 161 seg37/60 517 999 dummy45 ?404 1079 2 im2 ?811 ?079 62 osc1 1995 ?079 119 com15/10 5230 766 162 seg38/59 436 999 dummy46 ?484 1079 3 im1 ?627 ?079 63 vcc 2098 ?079 120 com16/9 5230 847 163 seg39/58 355 999 dummy47 ?565 1079 4 im0/id ?443 ?079 64 vcc 2179 ?079 dummy28 5230 927 164 seg40/57 275 999 dummy48 ?646 1079 5 vccdum ?340 ?079 65 vcc 2260 ?079 dummy29 5230 1079 165 seg41/56 194 999 dummy49 ?726 1079 6 opoff ?259 ?079 66 vcc 2340 ?079 dummy30 5032 1079 166 seg42/55 113 999 dummy50 ?807 1079 7 test ?075 ?079 67 vcc 2421 ?079 dummy31 4952 1079 167 seg43/54 33 999 dummy51 ?888 1079 8 port2 ?972 ?079 68 vcc 2502 ?079 dummy32 4871 1079 168 seg44/53 ?8 999 dummy52 ?968 1079 9 port2 ?891 ?079 69 vci 2605 ?99 dummy33 4791 1079 169 seg45/52 ?29 999 dummy53 ?049 1079 10 port1 ?788 ?079 70 vci 2686 ?99 dummy34 4710 1079 170 seg46/51 ?09 999 dummy54 ?129 1079 11 port1 ?707 ?079 71 vci 2766 ?99 dummy35 4629 1079 171 seg47/50 ?90 999 dummy1 ?309 1079 12 port0 ?604 ?079 72 vci 2847 ?99 dummy36 4549 1079 172 seg48/49 ?70 999 dummy2 ?309 955 13 port0 ?523 ?079 73 vci 2928 ?99 dummy37 4468 1079 173 seg49/48 ?51 999 221 coms2/s1 ?229 794 14 irq* ?420 ?079 74 c2+ 3008 ?99 dummy38 4387 1079 174 seg50/47 ?32 999 222 com24/1 ?229 713 15 irq* ?339 ?079 75 c2+ 3089 ?99 dummy39 4307 1079 175 seg51/46 ?12 999 223 com23/2 ?229 633 16 kst3 ?236 ?079 76 c2+ 3169 ?99 dummy40 4226 1079 176 seg52/45 ?93 999 224 com22/3 ?229 552 17 kst3 ?155 ?079 77 c2+ 3250 ?99 121 com17/8 4065 999 177 seg53/44 ?74 999 225 com21/4 ?229 471 18 kst2 ?052 ?079 78 c2 3331 ?99 122 com18/7 3984 999 178 seg54/43 ?54 999 226 com8/17 ?229 391 19 kst2 ?971 ?079 79 c2 3411 ?99 123 com19/6 3903 999 179 seg55/42 ?35 999 227 com7/18 ?229 310 20 kst1 ?868 ?079 80 c2 3492 ?99 124 com20/5 3823 999 180 seg56/41 ?016 999 228 com6/19 ?229 229 21 kst1 ?787 ?079 81 c2 3573 ?99 dummy41 3742 999 181 seg57/40 ?096 999 229 com5/20 ?229 149 22 kst0 ?684 ?079 82 c1+ 3653 ?99 dummy42 3662 999 182 seg58/39 ?177 999 230 com4/21 ?229 68 23 kst0 ?603 ?079 83 c1+ 3734 ?99 dummy43 3581 999 183 seg59/38 ?257 999 231 com3/22 ?229 ?3 24 db7/kin7 ?500 ?079 84 c1+ 3815 ?99 dummy44 3500 999 184 seg60/37 ?338 999 232 com2/23 ?229 ?3 25 db7/kin7 ?419 ?079 85 c1+ 3895 ?99 125 seg1/96 3420 999 185 seg61/36 ?419 999 233 com1/24 ?229 ?74 26 db6/kin6 ?316 ?079 86 c1+ 3976 ?99 126 set2/95 3339 999 186 seg62/35 ?499 999 234 coms1/s2 ?229 ?55 27 db6/kin6 ?236 ?079 87 c1 4056 ?99 127 seg3/94 3258 999 187 seg63/34 ?580 999 dummy3 ?309 ?33 28 db5/kin5 ?132 ?079 88 c1 4137 ?99 128 seg4/93 3178 999 188 seg64/33 ?661 999 dummy4 ?309 ?14 29 db5/kin5 ?052 ?079 89 c1 4218 ?99 129 seg5/92 3097 999 189 seg65/32 ?741 999 dummy5 ?309 ?95 30 db4/kin4 ?48 ?079 90 c1 4298 ?99 130 seg6/91 3016 999 190 seg66/31 ?822 999 dummy6 ?309 ?75 31 db4/kin4 ?68 ?079 91 c1 4379 ?99 131 seg7/90 2936 999 191 seg67/30 ?903 999 dummy7 ?309 ?56 32 db3/kin3 ?64 ?079 92 vlout 4460 ?99 132 seg8/89 2855 999 192 seg68/29 ?983 999 dummy8 ?309 ?37 33 db3/kin3 ?84 ?079 93 vlout 4540 ?99 133 seg9/88 2775 999 193 seg69/28 ?064 999 dummy9 ?309 ?17 34 db2/kin2 ?80 ?079 94 vlout 4621 ?99 134 seg10/87 2694 999 194 seg70/27 ?145 999 35 db2/kin2 ?00 ?079 95 vlout 4702 ?99 135 seg11/86 2613 999 195 seg71/26 ?225 999 36 db1/kin1 ?96 ?079 96 vlcd 4782 ?99 136 seg12/85 2533 999 196 seg72/25 ?306 999 37 db1/kin1 ?16 ?079 97 vlcd 4863 ?99 137 seg13/84 2452 999 197 seg73/24 ?386 999 38 db0/kin0 ?12 ?079 98 vlcd 4944 ?99 138 seg14/83 2371 999 198 seg74/23 ?467 999 39 db0/kin0 ?32 ?079 99 vlcd 5024 ?99 139 seg15/82 2291 999 199 seg75/22 ?548 999 40 reset* ?8 ?079 dummy25 5230 ?079 140 seg16/81 2210 999 200 seg76/21 ?628 999 41 reset* 52 ?079 dummy26 5230 ?53 141 seg17/80 2129 999 201 seg77/20 ?709 999 42 cs* 156 ?079 dummy27 5230 ?72 142 seg18/79 2049 999 202 seg78/19 ?790 999 43 cs* 236 ?079 100 v1out 5230 ?92 143 seg19/78 1968 999 203 seg79/18 ?870 999 44 rs 339 ?079 101 v1out 5230 ?11 144 seg20/77 1887 999 204 seg80/17 ?951 999 45 rs 420 ?079 102 v2out 5230 ?31 145 seg21/76 1807 999 205 seg81/16 ?032 999
hd66724/hd66725 13 chip-on-glass (cog) routing example com21/4 com22/3 com23/2 com24/1 coms2/s1 seg72/1 seg71/2 seg70/3 seg69/4 seg68/5 seg67/6 seg66/7 seg65/8 seg64/9 seg63/10 seg62/11 seg61/12 seg60/13 seg59/14 seg58/15 seg57/16 seg56/17 seg55/18 seg54/19 seg53/20 seg52/21 seg51/22 seg50/23 seg49/24 seg48/25 seg47/26 seg46/27 seg45/28 seg44/29 seg43/30 seg42/31 seg41/32 seg40/33 seg39/34 seg38/35 seg37/36 seg36/37 seg35/38 seg34/39 seg33/40 seg32/41 seg31/42 seg30/43 seg29/44 seg28/45 seg27/46 seg26/47 seg25/48 seg24/49 seg23/50 seg22/51 seg21/52 seg20/53 seg19/54 seg18/55 seg17/56 seg16/57 seg15/58 seg14/59 seg13/60 seg12/61 seg11/62 seg10/63 seg9/64 seg8/65 seg7/66 seg6/67 seg5/68 seg4/69 seg3/70 seg2/71 seg1/72 com20/5 com19/6 com18/7 com17/8 im0/id test gnddum im2 v cc dum opoff com8/17 com7/18 com6/19 com5/20 com4/21 com3/22 com2/23 com1/24 coms1/s2 com16/9 com15/10 com14/11 com13/12 com12/13 com11/14 com10/15 com9/16 vtest3 vtest2 vtest1 v5out v4out v3out v2out v1out db7/kin7 kst2 kst3 irq * port0 port1 port2 kst1 kst0 db6/kin6 db5/kin5 db4/kin4 db3/kin3 db2/kin2 db1/kin1 db0/kin0 reset * cs * rs r3 r2 r1 v cc v ci c2+ c2- c1+ c1- vlout v lcd osc1 osc2 im1 hd66724 (top view) x y ?clock-synchronized serial bus ?unused key scan ?unused port output ?quadruple booster ?internal operational amplifier e/wr * /scl rw/rd * /sda gnd
hd66724/hd66725 14 tcp dimensions (hd66724ta0) coms1/s2 com1/24 com8/17 seg72/1 seg1/72 com20/5 com9/16 dummy 0.50p x (48 ?1) = 23.5 mm 0.26p x (100 ?1) = 25.74 mm 0.26-mm pitch lcd driver i/o, power supply hitachi hitachi hd66724 hd66724 com21/4 com24/1 coms2/s1 dummy im2 im1 im0/id opoff test port2 kst3 kst2 kst1 kst0 db7/kin7 db6/kin6 db5/kin5 db4/kin4 db3/kin3 db2/kin2 db1/kin1 db0/kin0 reset* cs* rs e/wr*/scl rw/rd*/sda gnd osc2 osc1 vcc vci c2+ c2- c1+ c1- vlout vlcd v1out v2out v3out v4out v5out port1 port0 irq* vtest1 vtset2 vtest3 r3 r2 r1 vtest3 0.50-mm pitch
hd66724/hd66725 15 tcp dimensions (hd66725ta0) coms1/s2 com1/24 com8/17 seg96/1 seg1/96 com20/5 com9/16 dummy 0.65p x (50 ?1) = 31.85 mm 0.25p x (126 ?1) = 31.25 mm 0.25-mm pitch lcd driver power supply, i/o hitachi hitachi hd66725 hd66725 com21/4 com24/1 coms2/s1 dummy im2 im1 im0/id opoff test port2 kst3 kst2 kst1 kst0 db7/kin7 db6/kin6 db5/kin5 db4/kin4 db3/kin3 db2/kin2 db1/kin1 db0/kin0 reset* cs* rs e/wr*/scl rw/rd*/sda gnd osc2 osc1 vcc vci c2+ c2- c1+ c1- vlout vlcd v1out v2out v3out v4out v5out port1 port0 irq* vtest1 vtset2 vtest3 r3 r2 r1 vtest3 0.65-mm pitch dummy dummy nc nc note: the nc pin in the input side is electrically floating.
hd66724/hd66725 16 pin functions table 2 pin functional description signals number of pins i/o connected to functions im2, im1 2 i v cc or gnd selects the mpu interface mode: im2 ?nd ?nd ?cc ?cc im1 ?nd ?cc ?nd ?cc mpu interface clock-synchronized serial interface 68-system parallel bus interface setting inhibited 80-system parallel bus interface im0/id 1 i v cc or gnd inputs the id of the device id code for a serial bus interface. selects the transfer bus width for a parallel bus interface. gnd: 8-bit bus, vcc: 4-bit bus cs* 2 i mpu selects the hd66724/hd66725: low: hd66724/hd66725 are selected and can be accessed high: hd66724/hd66725 are not selected and cannot be accessed must be fixed at gnd level when not in use. rs 2 i mpu selects the register for a parallel bus interface. low: instruction high: ram access selects the key scan interrupt method in the standby period for a serial interface. monitors a total of eight keys connected to kst0 at the gnd level and monitors all keys at the vcc level to generate an interrupt. must be fixed at the vcc or gnd level. e/wr*/scl 2 i mpu inputs the serial transfer clock for a serial interface. fetches data at the rising edge of a clock. for a 68-system parallel bus interface, serves as an enable signal to activate data read/write operation. for an 80-system parallel bus interface, serves as a write strobe signal and writes data at the low level. rw/rd*/ sda 2 i/o or i mpu serves as the bidirectional serial transfer data for a serial interface. sends/receives data. for a 68-system parallel bus interface, serves as a signal to select data read/write operation. for an 80-system parallel bus interface, serves as a write strobe signal and reads data at the low level. irq* 2 o mpu generates the key scan interrupt signal. kst0 kst3 8 o key matrix generates strobe signals for latching scanned data from the key matrix at specific time intervals. available for a serial interface only. db0/kin0 db7/kin7 16 i or i/o key matrix or mpu samples key state from key matrix synchronously with strobe signals for a serial interface. serves as a bidirectional data bus for a parallel bus interface. for a four-bit bus, data transfer uses kin7/db7 kin4/db4; leave kin3/db3?in0/db0 disconnected.
hd66724/hd66725 17 table 2 pin functional description (cont) signals number of pins i/o connected to functions port0 port2 6 o general output general output ports. these ports cannot drive current such as for leds or backlighting control. boost the current using an external transistor. coms1/2, coms2/1 2 o lcd two common output signals for segment-icon display. com1/24 com24/1 24 o lcd common output signals for character/graphics display: com1 to com8 for the first line; com9 to com16 for the second line, and com17 to com24 for the third line. all the unused pins output deselection waveforms. in the sleep mode (slp = 1) or standby mode (stb = 1), all pins output gnd level. the cms bit can change the shift direction of the common signal. for example, if cms = 0, com1/24 is com1. if cms = 1, com1/24 is com24. seg1/72 seg72/1 (hd66724) 72 o lcd segment output signals for segment-icon display and character/graphics display. in the sleep mode (slp = 1) or standby mode (stb = 1), all pins output gnd level. seg1/96 seg96/1 (hd66725) 96 the sgs bit can change the shift direction of the segment signal. for example, if sgs = 0, seg1/72 (96) is seg1. if sgs = 1, seg1/72 (96) is seg72 (96). v1out v5out 10 o or i open or external bleeder-resistor used for output from the internal operational amplifiers when they are used (opoff = gnd); attach a capacitor to stabilize the output. when the amplifiers are not used (opoff = v cc ), v1 to v5 voltages can be supplied to these pins externally. v lcd 4 power supply power supply for lcd drive. v lcd ?gnd = 6.5 v max. v cc , gnd 14 power supply v cc : +1.8 v to +5.5 v; gnd (logic): 0 v osc1, osc2 2 i or o oscillation resistor or clock for r-c oscillation using an external resistor, connect an external resistor. for r-c oscillation using an internal resistor, connect r1?3 to osc2 and leave osc1 disconnected. for external clock supply, input clock pulses to osc1. r1?3 3 o osc2 for r-c oscillation using an internal resistor, adjust the internal resistor value. fluctuation of the resistor value is 30% of the reference value. care must be taken to avoid fluctuation of the frame frequency in crystal display drive operation. vci 5 i power supply inputs a reference voltage and supplies power to the booster; generates the liquid crystal display drive voltage from the operating voltage. vci = 0 v to 3.0 v v cc must be left disconnected when the booster is not used.
hd66724/hd66725 18 table 2 pin functional description (cont) signals number of pins i/o connected to functions vlout 4 o v lcd pin/booster capacitance potential difference between vci and gnd is boosted twice or three times and then output. magnitude of boost is selected by instruction. c1+, c1 10 booster capacitance external capacitance should be connected here when using the double or triple booster. c2+, c2 8 booster capacitance external capacitance should be connected here when using the triple booster. must be left disconnected only when using the double booster. reset* 2 i mpu or external r-c circuit reset pin. initializes the lsi when low. must reset after power-on. opoff 1 i v cc or gnd turns the internal operational amplifier off when opoff = v cc , and turns it on when opoff = gnd. if the amplifier is turned off (opoff = v cc ), v1 to v5 must be supplied to the v1out to v5out pins. vccdum 1 o input pins outputs the internal v cc level; shorting this pin sets the adjacent input pin to the v cc level. gnddum 1 o input pins outputs the internal gnd level; shorting this pin sets the adjacent input pin to the gnd level. test 1 i gnd test pin. must be fixed at gnd level. vtest1 vtest3 3 test pins. must be left disconnected.
hd66724/hd66725 19 block function description system interface the hd66724/hd66725 have five types of system interfaces, and a clock-synchronized serial, a 68-system 4-bit/8-bit bus, and a 80-system 4-bit/8-bit bus. the interface mode is selected by the im2-0 pins. the key scan of the hd66724/hd66725 are not available for the 4-bit/8-bit bus interface. instead, use the clock- synchronized serial interface. the hd66724/hd66725 have two 8-bit registers: an instruction register (ir) and a data register (dr). the ir stores instruction codes, such as clear display, display control, and address information for the display data ram (ddram), character generator ram (cgram), and segment ram (segram). the dr temporarily stores the data to be written to and read from the ddram, cgram, or segram. the data written to the dr from the mpu is automatically written to the ddram, cgram, or segram by internal operation. since the data is read from the ram through the dr, the first read data is invalid and the second read data is valid. after reading, the data in ddram, cgram, or segram at the next address is sent to the dr for the next reading from the mpu. execution time for instruction excluding clear display is 0 clock cycle and instructions can be written in succession. table 3 register selection by rs and r/w bits r/w bits rs bits operations 0 0 writes an instruction to the ir 1 0 reads key scan data (scan0-3) 0 1 writes the data to the dr to ddram, cgram, or segram 1 1 reads the data from the ddram, cgram, or segram to dr key scan registers (scan0 to scan3) the key matrix scanner senses and holds the key states at each rising edge of key strobe signals kst0 to kst3 that are output by the hd66724/hd66725. after passing through the key matrix, these strobe signals are used to sample the key states on eight inputs from kin0 to kin7, enabling up to 32 keys to be scanned. key states kin0 to kin7 are sampled by key strobe signal kst0 and latched into register scan0. similarly, the data sampled by strobe signals kst1 to kst3 is latched into registers scan1 to scan3, respectively. for details, see the key scan control section. general output ports (port0 to port 2) the hd66724/hd66725 have three general output ports. these ports control drive current such as that for leds or backlighting by using the current boosted by an external transistor.
hd66724/hd66725 20 address counter (ac) the address counter (ac) assigns addresses to ddram, cgram, or segram. when an address set instruction is written into the ir, the address information is sent from the ir to the ac. selection of ddram, cgram, and segram is also determined concurrently by the ram select bit (rm1/0). after writing into (reading from) ddram, cgram, or segram, the ac is automatically incremented by 1 (or decremented by 1). the cursor display position is determined by the address counter value. display data ram (ddram) the display data ram (ddram) stores display data represented in 8-bit character codes in the character display mode. its capacity is 80 8 bits, or 80 characters, which is equivalent to an area of 16 characters 5 lines. any number of display lines (lcd drive duty ratio) from 1 to 3 can be selected by software. here, assignment of ddram addresses is the same for all display modes (table 5). the line to be displayed at the top of the display (display-start line) can also be selected by register settings. the graphics display mode does not use the data in the ddram. character generator rom (cgrom) the character generator rom (cgrom) generates 6 8-dot character patterns from 8-bit character codes. it is equipped with a memory bank to generate 240 character patterns or 192 character patterns, which can be switched according to applications. for details, see the cgrom bank switching function section. table 6 illustrates the relation between character codes and character patterns for the hitachi standard cgrom. user-defined character patterns are also available using a mask-programmed rom (see the modifying character patterns section). character generator ram (cgram) the character generator ram (cgram) allows the user to redefine the character patterns in the character display mode. up to 64 character patterns of 6 x 8-dot characters can be simultaneously displayed. the ddram-specified character code can be selected to display one of these user font patterns. the cgram serves as a ram to store 72 x 24-dot (96 x 24-dot) bit pattern data in the graphics display mode. here, display patterns are directly written to the cgram. character codes set in the ddram are not used. for details, see the graphics display function section. segment ram (segram) the segment ram (segram) is used to enable control of segments such as icons and marks through the user program. segments and characters are driven by a multiplexing drive method. the segram has a capacity of 96 2 bits, to control the display of a maximum of 144 (192) icons and marks. while coms1 and coms2 outputs are being selected, the segram is read and segments (icons and marks) are displayed by a multiplexing drive method (72 (96) segments each during coms1 and coms2 selection).
hd66724/hd66725 21 bits in segram corresponding to segments to be displayed are directly set by the mpu, regardless of the contents of ddram and cgram. timing generator the timing generator generates timing signals for the operation of internal circuits such as ddram, cgrom, cgram, and segram. the ram read timing for display and internal operation timing by mpu access are generated separately to avoid interference with one another. this prevents flickering in areas other than the display area when writing the data to the ddram, for example. cursor/blink control circuit the cursor/blink (or black-white reversed) control is used to create a cursor or a flashing area on the display in a position corresponding to the location stored in the address counter (ac). cursor position display position ddram address note: the cursor/blink or black-white reversed control is also active when the address counter indicates the cgram or segram. however, it has no effect on the display. 12345678 11 910 12 00 01 02 03 04 05 06 07 0a 08 09 0b figure 1 cursor position and ddram address (when ac = 08h) oscillation circuit (osc) the hd66724/hd66725 can provide r-c oscillation simply through the addition of an external oscillation- resistor between the osc1 and osc2 pins. the appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. internal resistors can be used for r-c oscillation. if this is done, care must be taken due to variations in the oscillation frequency caused by fluctuations in internal-resistor values. clock pulses can also be supplied externally. since r-c oscillation stops during the standby mode, current consumption can be reduced. for details, see the oscillation circuit section. liquid crystal display driver circuit the liquid crystal display driver circuit consists of 26 common signal drivers (com1 to com24, coms1, coms2) and 72 (96) segment signal drivers (seg1 to seg72 (96)). when the number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output deselection waveforms.
hd66724/hd66725 22 the character pattern data is sent serially through a 72-bit (96-bit) shift register and latched when all needed data has arrived. the latched data then enables the segment signal drivers to generate drive waveform outputs. the shift direction of 72-bit (96-bit) data can be changed by the sgs bit. the shift direction for the common driver can also be changed by the cms bit by selecting an appropriate direction for the device mounting configuration. when multiplexing drive is not used, or during the standby or sleep mode, all the above common and segment signal drivers output the gnd level, halting the display. booster (dc-dc converter) the booster doubles or triples a voltage input to the vci pin. with this, both the internal logic units and lcd drivers can be controlled with a single power supply. boost output level from single to triple boost can be software-selected. for details, see the power supply for liquid crystal display drive section. v-pin voltage follower a voltage follower for each voltage level (v1 to v5) reduces current consumption by the lcd drive power supply circuit. no external resistors are required because of the internal bleeder-resistor, which generates different levels of lcd drive voltage. this internal bleeder-resistor can be software-specified from 1/2 bias to 1/6.5 bias, according to the liquid crystal display drive duty value. the voltage followers can be turned off while multiplexing drive is not being used. for details, see the power supply for liquid crystal display drive section. contrast adjuster the contrast adjuster can be used to adjust lcd contrast in 32 steps by varying the lcd drive voltage by software. this can be used to select an appropriate lcd brightness or to compensate for temperature. table 4 ddram addresses and display positions dis- play line 1st char. 2nd char. 3rd char. 4th char. 5th char. 6th char. 7th char. 8th char. 9th char. 10th char. 11th char. 12th char. 13th char. 14th char. 15th char. 16th char. 1st 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 2nd 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 3rd 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 4th 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 5th 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f note: when sgs = 0, seg 1/72 (96) to seg 6/67 (91) appear at the first character at the extreme left of the screen. when sgs = 1, seg 72 (96)/1 to seg 67 (91)/6 appear at the first character at the extreme left of the screen.
hd66724/hd66725 23 table 5 display-line modes, display-start line, and ddram addresses display-start lines display- line mode duty ratio common pins 1st line (sn = 000) 2nd line (sn = 001) 3rd line (sn = 010) 4th line (sn = 011) 5th line (sn = 100) 1-line (nl = 001) 1/10 com1 com8 00h?fh 10h?fh 20h?fh 30h?fh 40h?fh 2-line (nl = 010) 1/18 com1 com8 00h?fh 10h?fh 20h?fh 30h?fh 40h?fh 2-line (nl = 010) 1/18 com9 com16 10h?fh 20h?fh 30h?fh 40h?fh 00h?fh 3-line (nl = 011) 1/26 com1 com8 00h?fh 10h?fh 20h?fh 30h?fh 40h?fh 3-line (nl = 011) 1/26 com9 com16 10h?fh 20h?fh 30h?fh 40h?fh 00h?fh 3-line (nl = 011) 1/26 com17 com24 20h?fh 30h?fh 40h?fh 00h?fh 10h?fh
hd66724/hd66725 24 table 6 cgrom memory bank 0 (rom bit = 0) cgram (1) cgram (16) cgram (15) cgram (14) cgram (13) cgram (12) cgram (11) cgram (10) cgram (9) cgram (8) cgram (7) cgram (6) cgram (5) cgram (4) cgram (3) cgram (2) x 0 x f x e x d x c x b x a x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y a y b y c y d y e y f y 0 y lower bits upper bits
hd66724/hd66725 25 table 7 cgrom memory bank 1 (rom bit = 1) cgram (1) cgram (16) cgram (15) cgram (14) cgram (13) cgram (12) cgram (11) cgram (10) cgram (9) cgram (8) cgram (7) cgram (6) cgram (5) cgram (4) cgram (3) cgram (2) cgram (33) cgram (48) cgram (47) cgram (46) cgram (45) cgram (44) cgram (43) cgram (42) cgram (41) cgram (40) cgram (39) cgram (38) cgram (37) cgram (36) cgram (35) cgram (34) cgram (49) cgram (64) cgram (63) cgram (62) cgram (61) cgram (60) cgram (59) cgram (58) cgram (57) cgram (56) cgram (55) cgram (54) cgram (53) cgram (52) cgram (51) cgram (50) x 0 x f x e x d x c x b x a x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y a y b y c y d y e y f y lower upper cgram (17) cgram (32) cgram (31) cgram (30) cgram (29) cgram (28) cgram (27) cgram (26) cgram (25) cgram (24) cgram (23) cgram (22) cgram (21) cgram (20) cgram (19) cgram (18) 0 y 1 y bits bits
hd66724/hd66725 26 cgram address map table 8 relationship between character display mode (gr = 0) and cgram address font bank memory bank: rom = 0, 1 character code "00"h "01"h "02"h "03"h "04"h "05"h "06"h "07"h "08"h "09"h "0a"h "0b"h "0c"h "0d"h "0e"h "0f"h cgram address (hex) 000 to 005 006 to 00b 00c to 011 012 to 017 018 to 01d 01e to 023 024 to 029 02a to 02f 030 to 035 036 to 03b 03c to 041 042 to 047 048 to 04d 04e to 053 054 to 059 05a to 05f font bank memory bank: rom = 1 character code "10"h "11"h "12"h "13"h "14"h "15"h "16"h "17"h "18"h "19"h "1a"h "1b"h "1c"h "1d"h "1e"h "1f"h cgram address (hex) 100 to 105 106 to 10b 10c to 111 112 to 117 118 to 11d 11e to 123 124 to 129 12a to 12f 130 to 135 136 to 13b 13c to 141 142 to 147 148 to 14d 14e to 153 154 to 159 15a to 15f font bank memory bank: rom = 1 character code "80"h "81"h "82"h "83"h "84"h "85"h "86"h "87"h "88"h "89"h "8a"h "8b"h "8c"h "8d"h "8e"h "8f"h cgram address (hex) 200 to 205 206 to 20b 20c to 211 212 to 217 218 to 21d 21e to 223 224 to 229 22a to 22f 230 to 235 236 to 23b 23c to 241 242 to 247 248 to 24d 24e to 253 254 to 259 25a to 25f font bank memory bank: rom = 1 character code "90"h "91"h "92"h "93"h "94"h "95"h "96"h "97"h "98"h "99"h "9a"h "9b"h "9c"h "9d"h "9e"h "9f"h cgram address (hex) 300 to 305 306 to 30b 30c to 311 312 to 317 318 to 31d 31e to 323 324 to 329 32a to 32f 330 to 335 336 to 33b 33c to 341 342 to 347 348 to 34d 34e to 353 354 to 359 35a to 35f notes: 1. in the character display mode (gr = 0), cgram font pattern is displayed using character codes set to ddram as per the above table. in the graphics display mode (gr = 1), cgram data is displayed irrespective of the ddram set data (character code). 2. when the memory bank switching bit generates rom = 0, cgram fonts for 16 character codes "00"h to "0f"h can be displayed. when rom = 1, cgram fonts for 64 character codes "00"h to "1f"h and "80"h to "9f"h can be displayed.
hd66724/hd66725 27 table 9 relationship between cgram address and character pattern (cgram data) 1111 000 001 002 003 004 005 006 007 008 009 00a 00b 00c 35a 35b 35c 35d 35e 35f db0 db1 db2 db3 db4 db5 db6 db7 0 1 1 1 1 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 "00"h "01"h "8f"h 1 0 0 0 0 0 0 0 0 notes: 1. the least significant bit (lsb) of write data is displayed on the first line. the most significant bit (msb) is displayed on the 8th raster-row. 2. the 8th raster-row is the cursor position and its display is formed by a logical or with the cursor. 3. a set bit in the cgram data corresponds to display selection (lit) and 0 to non-selection (unlit). character code cgram address table 10 relationship between display position and cgram address in graphics display mode (gr = 1) display line 1st char. 2nd char. 3rd char. 4th char. 5th char. 6th char. 7th char. 8th char. 9th char. 10th char. 11th char. 12th char. 13th char. 14th char. 15th char. 16th char. 1st 000 to 005 006 to 00b 00c to 011 012 to 017 018 to 01d 01e to 023 024 to 029 02a to 02f 030 to 035 036 to 03b 03c to 041 042 to 047 048 to 04d 04e to 053 054 to 059 05a to 05f 2nd 100 to 105 106 to 10b 10c to 111 112 to 117 118 to 11d 11e to 123 124 to 129 12a to 12f 130 to 135 136 to 13b 13c to 141 142 to 147 148 to 14d 14e to 153 154 to 159 15a to 15f 3rd 202 to 205 206 to 20b 20c to 211 212 to 217 218 to 21d 21e to 223 224 to 229 22a to 22f 230 to 235 236 to 23b 23c to 241 242 to 247 248 to 24d 24e to 253 254 to 259 25a to 25f 4th 303 to 305 306 to 30b 33c to 311 312 to 317 318 to 31d 31e to 323 324 to 329 32a to 32f 330 to 335 336 to 33b 33c to 341 342 to 347 348 to 34d 34e to 353 354 to 359 35a to 35f notes: 1. in the graphic display mode (gr = 1), graphics pattern is displayed using bitmap data set to cgram as per the above table. 2. each display character and display line are converted to 6-dot width/character and 8 dots/line, respectively. 3. the 4th line is displayed by vertical smooth scroll operation.
hd66724/hd66725 28 table 11 relationship between cgram address and screen display position in graphics display mode (gr = 1) (hd66724) db0 000 db1 db2 db3 db4 db5 db6 db7 001 002 003 004 005 006 007 008 009 00a 00b 00c 00d 00e 00f 010 046 047 045 044 043 com1 com2 com3 com4 com5 com6 com7 com8 db0 100 db1 db2 db3 db4 db5 db6 db7 101 102 103 104 105 106 107 108 109 10a 10b 10c 10d 10e 10f 110 146 147 145 144 143 com9 com10 com11 com12 com13 com14 com15 com16 db0 200 db1 db2 db3 db4 db5 db6 db7 201 202 203 204 205 206 207 208 209 20a 20b 20c 20d 20e 20f 210 246 247 245 244 243 com17 com18 com19 com20 com21 com22 com23 com24 seg1/72 seg2/71 seg3/70 seg4/69 seg5/68 seg6/67 seg7/66 seg8/65 seg9/64 seg10/63 seg11/62 seg12/61 seg13/60 seg14/59 seg15/58 seg16/57 seg17/56 seg68/5 seg69/4 seg70/3 seg71/2 seg72/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00000 00000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 0 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 000 000 000 0000 00 00 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 00 0 00 0 00 0 00 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 0 0 0 0 0000000000000000 00000 00 0 000 000 0 0 0 0 0 0 0 0 0 0 0 0 0 00000 0 000 000 0 00 00 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 (hex) (hex) (hex) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 047 046 045 044 043 042 041 040 03f 02e 03d 03c 03b 03a 039 038 037 001 000 002 003 004 sgs="0" sgs="1" sgs="0" sgs="1" 147 146 145 144 143 142 141 140 13f 13e 13d 13c 13b 13a 139 138 137 101 100 102 103 104 sgs="0" sgs="1" 247 246 245 244 243 242 241 240 23f 23e 23d 23c 23b 23a 239 238 237 201 200 203 204 205 notes: 1. in the graphics display mode (gr=1), the cgram data is displayed irrespective of the ddram set data. 2. the hd66725 can display addresses from 000h to 35fh. 3. a set bit in the cgram data corresponds to display selection (lit) and 0 to non-selection (unlit). segment driver segment common address address address
hd66724/hd66725 29 segram address map table 12 relationship between segram address and screen display position (hd66724) db0 00 db1 db2 db7 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 46 47 45 44 43 coms1 coms2 seg1/72 seg2/71 seg3/70 seg4/69 seg5/68 seg6/67 seg7/66 seg8/65 seg9/64 seg10/63 seg11/62 seg12/61 seg13/60 seg14/59 seg15/58 seg16/57 seg17/56 seg68/5 seg69/4 seg70/3 seg71/2 seg72/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 (hex) db3 db4 db5 db6 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 47 46 45 44 43 42 41 40 3f 3e 3d 3c 3b 3a 39 38 37 01 00 02 03 04 sgs=0 segment driver sgs=1 segment common address note: the hd66725 can display addresses from 00h to 5fh. table 13 relationship between segment driver output pin and segment display function (hd66724) when sgs = 0 when sgs = 1 segment output control seg1/72, seg4/69, seg7/66, seg10/63, seg13/60, seg16/57, seg19/54, seg22/51, seg25/48, seg28/45, seg31/42, seg34/39, seg37/36, seg40/33, seg43/30, seg46/27, seg49/24, seg52/21, seg55/18, seg58/15, seg61/12, seg64/9, seg67/6, seg70/3 seg72/1, seg69/4, seg66/7, seg63/10, seg60/13, seg57/16, seg54/19, seg51/22, seg48/25, seg45/28, seg42/31, seg39/34, seg36/37, seg33/40, seg30/43, seg27/46, seg24/49, seg21/52, seg18/55, seg15/58, seg12/61, seg9/64, seg6/67, seg3/70 grayscale segment display allowed (reflective color segment supported) output pins other than above output pins other than above segment blinking allowed
hd66724/hd66725 30 table 14 relationship between segment driver output pin and segment display function (hd66725) when sgs = 0 when sgs = 1 segment output control seg1/96, seg4/93, seg7/90, seg10/87, seg13/84, seg16/81, seg19/78, seg22/75, seg25/72, seg28/69, seg31/66, seg34/63, seg37/60, seg40/57, seg43/54, seg46/51, seg49/48, seg52/45, seg55/42, seg58/39, seg61/36, seg64/33, seg67/30, seg70/27, seg73/24, seg74/21, seg79/18, seg82/15, seg85/12, seg88/9, seg91/6, seg94/3 seg96/1, seg93/4, seg90/7, seg87/10, seg84/13, seg81/16, seg78/19, seg75/22, seg72/25, seg69/28, seg66/31, seg63/34, seg60/37, seg57/40, seg54/43, seg51/46, seg48/49, seg45/52, seg42/55, seg39/58, seg36/61, seg33/64, seg30/67, seg27/70, seg24/73, seg21/76, seg18/79, seg15/82, seg12/85, seg9/88, seg6/91, seg3/94 grayscale segment display allowed (reflective color segment supported) output pins other than above output pins other than above segment blinking allowed note: for details, see the reflective color mark/blink mark display section. table 15 relationship between segram data and grayscale control segment display segram data setting effective applied voltage segram data setting effective applied voltage db3 db2 db1 db0 for coms1 segment db7 db6 db5 db4 for coms2 segment 0 0 0 0 0 (always unlit) 0 0 0 0 0 (always unlit) 0 0 0 1 1 (always lit) 0 0 0 1 1 (always lit) 0 0 1 0 0.34 (grayscale display) 0 0 1 0 0.34 (grayscale display) 0 0 1 1 0.38 (grayscale display) 0 0 1 1 0.38 (grayscale display) 0 1 0 0 0.41 (grayscale display) 0 1 0 0 0.41 (grayscale display) 0 1 0 1 0.44 (grayscale display) 0 1 0 1 0.44 (grayscale display) 0 1 1 0 0.47 (grayscale display) 0 1 1 0 0.47 (grayscale display) 0 1 1 1 0.50 (grayscale display) 0 1 1 1 0.50 (grayscale display) 1 0 0 0 (blink display) * 1 1 0 0 0 (blink display) * 1 1 0 0 1 0.53 (grayscale display) 1 0 0 1 0.53 (grayscale display) 1 0 1 0 0.56 (grayscale display) 1 0 1 0 0.56 (grayscale display) 1 0 1 1 0.59 (grayscale display) 1 0 1 1 0.59 (grayscale display) 1 1 0 0 0.63 (grayscale display) 1 1 0 0 0.63 (grayscale display) 1 1 0 1 0.66 (grayscale display) 1 1 0 1 0.66 (grayscale display) 1 1 1 0 0.69 (grayscale display) 1 1 1 0 0.69 (grayscale display) 1 1 1 1 0.72 (grayscale display) 1 1 1 1 0.72 (grayscale display) note: blinking is provided by repeatedly turning on the segment for 32 frames and turning it off for the next 32 frames.
hd66724/hd66725 31 table 16 relationship between segram data and blinking control segment display (blinking control segment driver) segram data setting lcd display control for segram data setting lcd display control for db3 db2 db1 db0 coms1 segment db7 db6 db5 db4 coms2 segment 0* 1 * 1 0 0 (always unlit) 0 * 1 * 1 0 0 (always unlit) 0* 1 * 1 1 1 (always lit) 0 * 1 * 1 1 1 (always lit) 1* 1 * 1 0 blinking display 1 * 1 * 1 0 blinking display 1* 1 * 1 1 double-speed blinking display 1* 1 * 1 1 double-speed blinking display notes: 1. 0 or 1. 2. blinking is provided by repeatedly turning on the segment for 32 frames and turning it off for the next 32 frames. 3. double-speed blinking is provided by repeatedly turning on the segment for 16 frames and turning it off for the next 16 frames.
hd66724/hd66725 32 modifying character patterns character pattern development procedure start write eprom art work ok ? masking trial sample ok ? sample evaluation hitachi user no no yes yes eprom hitachi ? determine character patterns create eprom address data listing computer processing create character pattern listing mass production evaluate character patterns figure 2 character pattern development procedure
hd66724/hd66725 33 the following operations correspond to the numbers listed in figure 2: 1. determine the correspondence between character codes and character patterns. 2. create a listing indicating the correspondence between eprom addresses and data. 3. program the character patterns into an eprom. 4. send the eprom to hitachi. 5. computer processing of the eprom is performed at hitachi to create a character pattern listing, which is sent to the user. 6. if there are no problems within the character pattern listing, a trial lsi is created at hitachi and samples are sent to the user for evaluation. when the user confirms that the character patterns are correctly written, hitachi will commence lsi mass production.
hd66724/hd66725 34 programming character patterns this section explains the correspondence between addresses and data used to program character patterns in eprom. programming to eprom: the hd66724/hd66725 character generator rom can generate 432 6 8-dot character patterns. table 17 shows the correspondence between the eprom address, data, and the character pattern. table 17 examples of correspondence between eprom address, data, and character pattern (6 8 dots) a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 000 00 1 010 011 100 101 11 0 111 1 000 1 o 4 o 3 o 2 o 1 o 0 1 0001 1 0001 01 010 0 0100 0 0100 00 1 00 0 0000 0 o 5 0 0 0 0 0 0 0 character code line position eprom address data lsb msb 0 0 0 0 0 0 0 0 0 rom bit a 11 a 12 0 0 1011001 notes: 1. eprom address: bit a12 corresponds to the cgrom memory bank switch bit ("rom"). 2. eprom address: bits a11 to a4 correspond to a character code. 3. eprom address: bits a2 to a0 specify the line position of the character pattern. eprom address bit a3 must be set to 0. 4. eprom data: bits o5 to o0 correspond to character pattern data. 5. areas which are lit (indicated by shading) are stored as 1, and unlit areas as 0. 6. the eighth raster-row is also stored in the cgrom, and must also be programmed. if the eighth raster-row is used for a cursor, this data must all be set to zero. 7. eprom data: bits o7 to o6 are invalid. 0 must be written in all bits. handling unused character patterns: 1. eprom data outside the character pattern area: this is ignored by character generator rom for display operation so any data is acceptable. 2. eprom data in cgram area: always fill with zeros. 3. treatment of unused user patterns in the hd66724/hd66725 eprom: depending on to the user application, these are handled in either of two ways:
hd66724/hd66725 35 a. when unused character patterns are not programmed: if an unused character code is written into ddram, all its dots are lit, because the eprom is filled with 1s after it is erased. b. when unused character patterns are programmed as 0s: nothing is displayed even if unused character codes are written into ddram. (this is equivalent to a space.) instructions outline only the instruction register (ir) and the data register (dr) of the hd66724/hd66725 can be controlled by the mpu. before starting internal operation of the hd66724/hd66725, control information is temporarily stored in these registers to allow interfacing with various peripheral control devices or mpus which operate at different speeds. the internal operation of the hd66724/hd66725 is determined by signals sent from the mpu. these signals, which include the register selection signal (rs), the read/write signal (r/w), and the data bus signal (db0 to db7), make up the hd66724/hd66725 instructions. there are five categories of instructions that: control the display control power management set internal ram addresses transfer data with the internal ram control key scan (when serial interface mode) normally, instructions that perform data transfer with the internal ram are used the most. however, auto- incrementation by 1 (or auto-decrementation by 1) of internal hd66724/hd66725 ram addresses after each data write can lighten the mpu program load. because instructions other than clear display instruction are executed in 0 cycle, instructions can be written in succeccion. while the clear display instruction is being executed for internal operation, or during reset, no instruction other than the key scan read instruction can be executed.
hd66724/hd66725 36 instruction descriptions key scan data read in the serial interface mode, the key scan data read instruction reads scan data in scan registers scan0 to scan3. following transfer of the start byte, scan data read operation starts from scan register scan0 and proceeds in the order of scan1, scan2, and scan3. when data read from scan 0 to scan3 is completed, the operation starts from scan0 again. for details, see the key scan control section. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 010 1 1 se2 se1 00 01 10 0 sq2 sq1 sq0 sse se4 se3 (sse = 0) (sse = 1) figure 3 key scan data read instruction clear display the clear display instruction writes space code 20h (the character pattern for character code 20h must be a blank pattern) into all ddram addresses. it then sets ddram address 0 into the address counter. it also sets i/d to 1 (increment mode) in the entry mode set instruction. since the execution of this instruction needs 85 clock cycles, do not send the next instruction during the execution time. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 00000001 figure 4 clear display instruction return home the return home instruction sets ddram address 0 into the address counter. the ddram contents do not change. the cursor or blinking goes to the top left of the display. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 00000010 figure 5 return home instruction
hd66724/hd66725 37 start oscillation the start oscillation instruction restarts the oscillator from the halt state in the standby mode. after issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (refer to the standby mode section.) r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 00000011 figure 6 start oscillation instruction driver output control cms: selects the output shift direction of a common driver. when cms = "0", com1/24 shifts to com1, and com24/1 to com24. when cms = "1", com1/24 shifts to com24, and com24/1 to com1. output position of a common driver shifts depending on the cen bit setting. for details, see the display on/off control section. sgs: selects the output shift direction of a segment driver. when sgs = "0", seg1/72 (96) shifts to seg1, and seg72 (96)/1 to seg72 (96). when sgs = "1", seg1/72 (96) shifts seg72 (96), and seg72 (96)/1 to seg1. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 0 0 0 0 0 1 cms sgs figure 7 driver output control instruction power control amp: when amp = 1, each voltage follower for the v1 to v5 pins and the booster are turned on. when amp = 0, current consumption can be reduced when the display is not being used. in this case, set bt1/0 = 00 for single boosting output. slp: when slp = 1, the hd66724/hd66725 enter the sleep mode, where the internal operations are halted except for the key scan function and the r-c oscillator, thus reducing current consumption. for details, refer to the sleep mode section. only the following instructions can be executed during the sleep mode. a. key scan data read b. key scan control (ire, kf1/0 bit) c. power control (amp, slp, and stb bits) d. port control (pt2-0 bits)
hd66724/hd66725 38 during the sleep mode, the other ram data and instructions cannot be updated although they are retained. stb: when stb = 1, the hd66724/hd66725 enter the standby mode, where display operation and key scan completely stop, halting all the internal operations including the internal r-c oscillator. further, no external clock pulses are supplied. this setting can be used as the system wake-up, because an interrupt is generated when a specific key is pressed. for details, refer to the standby mode section. only the following instructions can be executed during the standby mode. a. standby mode cancel (stb = 0) b. voltage follower circuit on/off (amp = 1/0) c. start oscillator d. key scan interrupt generation enabled/disabled (ire = 1/0) e. port control (pt2-0 bits) during the standby mode, the other ram data and instructions may be lost. to prevent this, they must be set again after the standby mode is canceled. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 0 0 0 0 1 amp slp stb figure 8 power control instruction contrast control 1/2 sw: switches the bit configuration for the contrast control instruction. sw = 0 corresponds to ct4 to ct0. sw = 1 corresponds to bt1/0 and bs2 to bs0. ct4?t0: when sw = 0 controls the lcd drive voltage (potential difference between v1 and gnd) to adjust contrast. a 32-step adjustment is possible. for details, refer to the contrast adjuster section. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 000 10 sw ct4 ct3 bt1 bt0 (sw = 0) (sw = 1) 00 000 11 ct1 ct0 bs1 bs0 (sw = 0) (sw = 1) ct2 bs2 figure 9 contrast control 1/2 instruction
hd66724/hd66725 39 v lcd v1 v2 v3 v4 v5 vr r r r 0 r r - + - + - + - + - + gnd hd66724/5 gnd figure 10 contrast adjuster
hd66724/hd66725 40 table 18 ct bits and variable resistor value of contrast adjuster ct set value variable ct set value variable ct4 ct3 ct2 ct1 ct0 resistor (vr) ct4 ct3 ct2 ct1 ct0 resistor (vr) 0 0 0 0 0 3.2 x r 1 0 0 0 0 1.6 x r 0 0 0 0 1 3.1 x r 1 0 0 0 1 1.5 x r 0 0 0 1 0 3.0 x r 1 0 0 1 0 1.4 x r 0 0 0 1 1 2.9 x r 1 0 0 1 1 1.3 x r 0 0 1 0 0 2.8 x r 1 0 1 0 0 1.2 x r 0 0 1 0 1 2.7 x r 1 0 1 0 1 1.1 x r 0 0 1 1 0 2.6 x r 1 0 1 1 0 1.0 x r 0 0 1 1 1 2.5 x r 1 0 1 1 1 0.9 x r 0 1 0 0 0 2.4 x r 1 1 0 0 0 0.8 x r 0 1 0 0 1 2.3 x r 1 1 0 0 1 0.7 x r 0 1 0 1 0 2.2 x r 1 1 0 1 0 0.6 x r 0 1 0 1 1 2.1 x r 1 1 0 1 1 0.5 x r 0 1 1 0 0 2.0 x r 1 1 1 0 0 0.4 x r 0 1 1 0 1 1.9 x r 1 1 1 0 1 0.3 x r 0 1 1 1 0 1.8 x r 1 1 1 1 0 0.2 x r 0 1 1 1 1 1.7 x r 1 1 1 1 1 0.1 x r bt1-0: when sw = 1, it switches the output of v5out between single, double, and triple boost. the liquid crystal display drive voltage level can be selected according to its drive duty ratio and bias. a lower amplification of the booster consumes less current. bs2-0: when sw = 1, it sets the crystal display drive bias value within the range of 1/4 to 1/6.5 bias. the liquid crystal display drive bias value can be selected according to its drive duty ratio and voltage. for details, see the liquid crystal display drive bias selector circuit section. table 19 bt bits and output level bt1 bt0 v5out output level 0 0 single boost (no boost) 0 1 double boost 1 0 triple boost 1 1 setting inhibited
hd66724/hd66725 41 table 20 bs bits and lcd drive bias value bs2 bs1 bs0 liquid crystal display drive bias value 0 0 0 1/6.5 bias drive 0 0 1 1/6 bias drive 0 1 0 1/5.5 bias drive 0 1 1 1/5 bias drive 1 0 0 1/4.5 bias drive 1 0 1 1/4 bias drive 1 1 0 inhibit 1 1 1 inhibit entry mode set rom: switches the cgrom memory bank in the character mode (gr = 0). uses bank 0 for display when rom = 0 and bank 1 for display when rom = 1. for details, see the cgrom bank switching function section. i/d: increments (i/d = 1) or decrements (i/d = 0) the ddram address by 1 when a character code is written into or read from ddram. the cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. the same applies to the writing and reading of cgram and segram. gr: activates the character mode when gr = 0. displays the font pattern on cgrom or cgram according to the character code written in ddram. activates the graphics mode when gr = 1. displays a given pattern according to the bitmap data written in cgram. in this case, data in ddram is not used for display. segment pattern display set to segram is enabled both in the character mode and graphics mode. for details, see the graphics display function section. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 0 0 1 0 0 i/d gr rom figure 11 entry mode set instruction cursor control b/w : when b/w is 1, the character at the cursor position is cyclically (every 32 frames) blink-displayed with black-white inversion. when b/w = 1 and lc = 1, all characters including the cursor on the display line appear with black-white inversion. the characters do not blink. for details, refer to the line-cursor display section. c: the cursor is displayed on the 8th raster-row when c is 1. the 6-dot cursor is ored with the character pattern and displayed on the 8th raster-row.
hd66724/hd66725 42 b: the character indicated by the cursor blinks when b is 1. the blinking is displayed as switching between all black dots and displayed characters every 32 frames. the cursor and blinking can be set to display simultaneously. when lc and b = 1, the blinking is displayed as switching between all white dots and displayed characters. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 0 0 1 0 1 b/w c b figure 12 cursor control instruction alternating display (every 32 frames) alternating display i) white-black inverting display example (when lc = 0) ii) 8th raster-row cursor displa y ii) blink display example figure 13 cursor control examples display on/off control d: display is on when d is 1 and off when d is 0. when off, the display data remains in ddram, and can be displayed instantly by setting d to 1. when d is 0, the display is off with the seg1 to seg72 (96) outputs, com1 to com24 outputs, and coms1/2 output set to the gnd level and off. because of this, the hd66724/hd66725 can control charging current for the lcd with ac driving. cen: switches the common driver position from com1 to com8. when cen = 1, it outputs the first line of com1 to com8 in the center of the screen. for details, see the partial-display-on function section. lc: when lc = 1, a cursor attribute is assigned to the line that contains the address counter (ac) value. cursor mode can be selected with the b/w, c, and b bits. refer to the line-cursor display section. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 00110d cen lc figure 14 display on/off control instruction
hd66724/hd66725 43 table 21 common driver pin function common driver pin function cen = 0 (normal output) cen = 1 (center output) common driver pin cms = 0 (normal display) cms = 1 (inverted display) cms = 0 (normal display) cms = 1 (inverted display) com1/24 com1 com24 com17 com16 com2/23 com2 com23 com18 com15 com3/22 com3 com22 com19 com14 com4/21 com4 com21 com20 com13 com5/20 com5 com20 com21 com12 com6/19 com6 com19 com22 com11 com7/18 com7 com18 com23 com10 com8/17 com8 com17 com24 com9 com9/16 com9 com16 com1 com8 com10/15 com10 com15 com2 com7 com11/14 com11 com14 com3 com6 com12/13 com12 com13 com4 com5 com13/12 com13 com12 com5 com4 com14/11 com14 com11 com6 com3 com15/10 com15 com10 com7 com2 com16/9 com16 com9 com8 com1 com17/8 com17 com8 com9 com24 com18/7 com18 com7 com10 com23 com19/6 com19 com6 com11 com22 com20/5 com20 com5 com12 com21 com21/4 com21 com4 com13 com20 com22/3 com22 com3 com14 com19 com23/2 com23 com2 com15 com18 com24/1 com24 com1 com16 com17 com1/2 coms1 coms2 coms1 coms2 com2/1 coms2 coms1 coms2 coms1
hd66724/hd66725 44 display line control nl2-0: specifies the display lines. display lines change the liquid crystal display drive duty ratio. ddram address mapping does not depend on the number of display lines. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 0 0 1 1 1 nl1 nl0 nl2 figure 15 display line control instruction table 22 nl bits and display lines nl2 nl1 nl0 display lines liquid crystal display drive duty ratio common driver used 0 0 0 segment display 1/2 duty coms1, coms2 0 0 1 one character line + segment display 1/10 duty com1-8, coms1, coms2 0 1 0 two character lines + segment display 1/18 duty com1-16, coms1, coms2 0 1 1 three character lines + segment display 1/26 duty com1-24, coms1, coms2 1 * * setting inhibited double-height display control dl3-1: specifies the double-height display for a given line. when dl1 = 1, the first line is displayed at double height. when dl2 = 1, the second line is displayed at double height. when dl3 = 1, the third line is displayed at double height. double-height display of multiple lines is possible. for details, see the double-height display section. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 0 1 0 0 0 dl3 dl2 dl1 figure 16 double-height display control instruction vertical scroll control 1/2 sn2-0: specifies the display start line output from com1. because ddram is assigned a 5-line display area, data is displayed sequentially from the first line to the fifth line then repeated from the first line again. sl2?: selects the top raster-row to be displayed (display-start raster-row) in the display-start line specified by sn2 to sn0. any raster-row from the first to eighth can be selected (table 24). this function
hd66724/hd66725 45 is used to achieve vertical smooth scrolling together with sn2 to sn0. for details, refer to the vertical smooth scroll section. during horizontal scrolling, the sn0 bit must be 0 (sn0 = 0). r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 0 100 1 sn1 sn0 00 010 1 0 sl2 sl1 sl0 sn2 figure 17 vertical scroll control 1/2 instruction table 23 sn bits and display-start lines sn2 sn1 sn0 display-start line 0 0 0 1st line 0 0 1 2nd line 1 1 0 3rd line 1 1 1 4th line 1 0 0 5th line 1 0 1 setting inhibited 1 1 0 setting inhibited 1 1 1 setting inhibited table 24 sl bits and display-start raster-row sl2 sl1 sl0 display-start raster-row 0 0 0 1st raster-row 0 0 1 2nd raster-row 0 1 0 3rd raster-row 0 1 1 4th raster-row 1 0 0 5th raster-row 1 0 1 6th raster-row 1 1 0 7th raster-row 1 1 1 8th raster-row
hd66724/hd66725 46 horizontal scroll control sse: when sse = 0, it selects se2 and se1 bits and when sse = 1, it selects se3 and se4 bits. se3-1: specifies the horizontal smooth scroll display for a given line. when se = 1, the first line is displayed in a horizontal scroll. when se = 1, the second line is displayed in a horizontal scroll. when se = 1, the third line is displayed in a horizontal scroll. when se = 4, the fourth line is displayed in a horizontal scroll. horizontal scroll display of multiple lines is possible. sq2-0: shifts the line to which horizontal smooth scroll is specified by units of 3 dots, up to 21 dots, to the left. for details, see the horizontal smooth scroll section. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 010 1 1 se2 se1 00 01 10 0 sq2 sq1 sq0 sse se4 se3 (sse = 0) (sse = 1) figure 18 horizontal scroll control instruction table 25 sq bits and display start line sq2 sq1 sq0 display start line 0 0 0 displayed with no shift 0 0 1 displayed with 3 dots shifted to the left 0 1 0 displayed with 6 dots shifted to the left 0 1 1 displayed with 9 dots shifted to the left 1 0 0 displayed with 12 dots shifted to the left 1 0 1 displayed with 15 dots shifted to the left 1 1 0 displayed with 18 dots shifted to the left 1 1 1 displayed with 21 dots shifted to the left key scan control ire: when ire = 1, it permits interrupts when a key is pressed. this causes interrupts to occur in the standby period when the oscillator clock is halted, as well as key scan interrupts during normal operation, allowing system wake-up. kf1-0: sets the key scan cycle. the following table shows the key scan pulse width and key scan cycle used when the oscillation frequency (fosc) is 32 khz, which depend on the oscillation frequency. for details, see the key scan control section.
hd66724/hd66725 47 r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 0 1 1 0 1 kf1 kf0 ire figure 19 key scan control instruction table 26 kf bits and key scan cycle kf1 kf0 key scan pulse width key scan cycle 0 0 0.25 ms 1.0 ms (32 clock cycles) 0 1 0.5 ms 2.0 ms (64 clock cycles) 1 0 1.0 ms 4.0 ms (128 clock cycles) 1 1 2.0 ms 8.0 ms (256 clock cycles) note: the data is a value obtained when the oscillation frequency (fosc) is 32 khz. the value depends on the oscillation frequency.
hd66724/hd66725 48 port control pt2-0: controls the output level of a port output pin (port2-port0). when pt0 = 0, it specifies the pot0 output to gnd and when pt0 = 1, to vcc. similarly, pt1 and pt2 bits control port1 and port2 output levels respectively. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 0 1 1 1 0 pt1 pt0 pt2 figure 20 port control instruction ram address set rm1-0: selects ddram, cgram, and segram. the selected ram is accessed with this setting. ad9-0: initially sets ram addresses to the address counter (ac). once ram data is accessed, the ac is automatically updated according to the i/d bit. this allows consecutive accesses without resetting addresses. ram address setting is not allowed in the sleep mode or standby mode. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 1 0 ad7 ad6 00 1 1 ad2 ad1 ad0 ad8 ad3 ad9 ad4 rm0 ad5 rm1 figure 21 ram address set instruction table 27 rm bits and ram selection rm1 rm0 ram selection 0 0 ddram 0 1 setting inhibited 1 0 cgram 1 1 segram
hd66724/hd66725 49 table 28 ad bits and ddram setting rm1/0 ad9-ad0 ddram setting 00 "000"h-"00f"h character code on the 1st line 00 "010"h-"01f"h character code on the 2nd line 00 "020"h-"02f"h character code on the 3rd line 00 "030"h-"03f"h character code on the 4th line 00 "040"h-"04f"h character code on the 5th line table 29 ad bits and cgram setting (gr = 0) rm1/0 ad9-ad0 cgram (1) setting in the character display mode (gr = 0) 10 "000"h-"05f"h font pattern of cgram characters (1) to (16) 10 "100"h-"15f"h font pattern of cgram characters (17) to (32) 10 "200"h-"25f"h font pattern of cgram characters (33) to (48) 10 "300"h-"35f"h font pattern of cgram characters (49) to (64) table 30 ad bits and cgram setting (gr = 1) rm1/0 ad9-ad0 cgram (1) (2) setting in the graphics display mode (gr = 1) 10 "000"h-"05f"h bitmap data for com1 to com8 10 "100"h-"15f"h bitmap data for com9 to com16 10 "200"h-"25f"h bitmap data for com17 to com24 10 "300"h?35f"h bitmap data for com25 to com32 table 31 ad bits and segram setting rm1/0 ad9-ad0 segram setting 11 "000"h-"05f"h segram display data
hd66724/hd66725 50 write data to ram wd7-0 : writes 8-bit data to ddram and cgram lower 2-bit data to segram. ddram/ cgram/ segram is selected by the previous specification of the rm 1/0bit. after a write, the address is automatically incremented or decremented by 1 according to the i/d bit setting in the entry mode set instruction. during the sleep and standby modes, ddram, cgram, or segram cannot be accessed. r/w rs db7 db0 0 1 db6 db5 db4 db3 db2 db1 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 figure 22 write data to ram instruction
hd66724/hd66725 51 read data from ram rd7-0 : reads the 8-bit data from ddram, cgram or segram. ddram/cgram/segram is selected by the previous specification of the rm 1/0 bit. in the parallel bus interface mode, the first-byte data read will be invalid immediately after the ram address is set, and the subsequent second-byte data will be read normally. in the serial interface mode, two bytes will be invalid immediately after the start byte, and the subsequent third-byte data will be read normally. for details, see the serial data transfer section. after a ddram read, the address is automatically incremented or decremented by 1 according to the i/d bit setting in the entry mode set instruction. r/w rs db7 db0 1 1 db6 db5 db4 db3 db2 db1 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 figure 23 read data from ram instruction address: n set dummy read (invalid data) read (data of address n) first byte second byte i) parallel bus interface mode address: n set dummy read (invalid data) read (data of address n) first byte third byte ii) serial interface mode start byte start byte dummy read (invalid data) second byte figure 24 ram read sequence
hd66724/hd66725 52 table 32 instruction list register code execu- tion name r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle *1 key scan data read 1 0 ksd reads key scan data (ksd). 0 no operation 0000 000 000no operation (nop). 0 clear display 0000 000 001 clears entire display and sets address 0 into the address counter. 85 return home 0000 000 010 sets ddram address 0 into the address counter. 0 start oscillator 0000 000 011 starts the oscillation standby mode. driver output control 0000 000 1cmssgs selects the common driver shift direction (cms) and segment driver shift direction (sgs). 0 power control 0000 001 ampslpstb turns on lcd power supply (amp), and sets the sleep mode (slp) and standby mode (stb). 0 contrast control 1 0000 010 swct4ct3 sets the register selection 0 bt1 bt0 (sw), upper contrast adjustment bits (ct4-3) or boost level (bt1/0). contrast control 2 0000 011 ct2ct1ct0 sets the lower contrast 0 bs2 bs1 bs0 adjustment bits (ct2-0) or lcd bias value (bs2-0). entry mode set 0000 100 romi/dgr sets the cgrom memory bank switching (rom), address update direction after ram access (i/d), and graphics mode (gr). 0 cursor control 0000 101 b/wcb sets black-white inverting cursor (b/w), 8th raster-row cursor (c), and blink cursor (b). 0 display on/off control 0000 110 dcenlc sets display on (d), centers the screen (cen), and displays the line cursor (lc). 0 display line control 0000 111 nl2nl1nl0 sets the number of display lines (nl2-0). 0 double-height display control 0001 000 dl3dl2dl1 specifies double-height display lines (dl3-1). 0 vertical scroll control 1 0001 001 sn2sn1sn0 sets the display-start line (sn2-0). 0 vertical scroll control 2 0001 010 sl2sl1sl0 sets the display-start raster- row (sl2-0). 0
hd66724/hd66725 53 table 31 instruction list (cont) register code execu- tion name r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle *1 horizontal scroll 0001 011 ssese2se1 specifies se1-4 bit selection 0 control 1 se4 se3 (sse) and the display line where horizontal scroll is applied (se1-4). horizontal scroll control 2 0001 100 sq2sq1sq0 specifies the amount of scroll dot shift (sq2-0) in horizontal smooth scroll. 0 key scan control 0001 101 irekf1kf0 sets the key scan interrupt (ire) and key scan cycle (kf1/0). 0 port control 0001 110 pt2pt1pt0 sets the general port output (pt2-0). 0 ram address set (upper bits) 0010 rm1rm0 ad9-6 (upper bits) sets the ram selection (rm1/0) and initial higher ram address to the address counter (ac). 0 ram address set (lower bits) 0011 ad5-0 (lower bits) sets the initial higher ram address to the address counter (ac). 0 write data to ram 0 1 write data writes data to ddram, cgram, or segram. 0 read data from ram 1 1 read data reads data from ddram, cgram, or segram. 0 note: 1. represented by the number of operating clock pulses; the execution time depends on the supplied clock frequency or the internal oscillation frequency. bit definition: cmc = 0: com1/24 => com1 sgs = 0: seg1/72 => seg1 amp = 1: operational amplifier and booster circuit on slp = 1: sleep mode stb = 1: standby mode sw = 0: ct4-0 access/sw = 1: bt1/0 and bs2-0 access ct4-0: contrast adjustment bt1/0: boost level selection (00: single, 01: double, 10: triple) bs2-0: lcd drive bias selection rom = 0: cgrom bank 0 selection/rom = 1: cgrom bank 1 selection id = 1: address increment id = 0: address decrement gr = 1: graphics display mode gr = 0: character display mode b/w = 1: black-white inverting cursor on
hd66724/hd66725 54 c = 1: 8th raster-row cursor on b = 1: blink cursor on d = 1: display on cen = 1: centering com1-8 lc = 1: cursor display for the all display lines including ac nl2-0: display line setting (000: 1/2 duty ratio, 001: 1/10 duty ratio, 010: 1/18 duty ratio, 011: 1/26 duty ratio) dl3-1: double-height line specifications (dl1: 1st line, dl2: 2nd line, dl3: 3rd line) sn2-0: display-start line (000: 1st line, 001: 2nd line, 010: 3rd line, 011: 4th line, 100: 5th line) sl2-0: display-start raster-row specifications (000: 1st raster-row...111: 8th raster-row) sse: se1-4 bit selection (sse = 0: se1/2 bit selection, sse = 1: se3/4 bit selection) se1-4: horizontal smooth scroll display line specifications (se1 = 1: 1st line, se2 = 1: 2nd line, se3 = 1: 3rd line, se4 = 1: 4th line) sq2-0: horizontal scroll dots specifications (000: 0-dot shift...111: 21-dot shift) ire = 1: key scan interrupt generation enabled kf1/0: key scan cycle set pt2-0: port output control (pt2 = 1: port2 = vcc, pt1 = 1: port1 = vcc, pt0 = 1: port0 = vcc) rm1/0: ram selection (00/01: ddram, 10: cgram, 11: segram) add9-0: ddram/cgram/segram address set (ddram: 000h-04fh, cgram: 000h-35fh, segram: 000h-047h)
hd66724/hd66725 55 reset function the hd66724/hd66725 are internally initialized by reset input. during initialization, the system executes a clear display instruction after reset is canceled. the system executes the other instructions during the reset period. because the busy flag (bf) indicates a busy state (bf = 1) during the reset period and execution of the clear display instruction following reset cancellation, no instruction or ram data access from the mpu is accepted. here, reset input must be held back for at least 1 ms, and an issuing instruction must wait for 1,000 clock cycles after reset is canceled because the display clearing continues after reset cancellation. instruction set initialization: 1. clear display executed (writes 20h to ddram) 2. return home executed (sets the address counter (ac) to 00h to select ddram) 3. start oscillator executed 4. driver output control (sgs = 0, cms = 0) 5. power control (amp = 0: lcd power off, slp = 0: sleep mode off, stb = 0: standby mode off) 6. single boost (bt1/0 = 00), 1/6.5 bias drive (bs2/1/0 = 000), weak contrast (ct4-0 = 00000) 7. entry mode set (rom = 0: cgrom bank 0, i/d = 1: increment by 1, gr = 0: character display mode) 8. cursor display off (b/w = 0, c = 0, b = 0) 9. display on/off control (d = 0: display off, cen = 0: normal position, lc = 0: line-cursor off) 10. display control (nl2/1/0 = 100: 1/34 duty ratio) 11. double-height display off (dl3/2/1 = 000) l2. vertical scroll control (sn2/1/0 = 000: first line displayed at the top, sl2/1/0: first raster-row displayed at the top of the first line) 13. horizontal scroll off (see = 0, se2/1 = 00, se4/3 = 00, sq2/1/0 = 000) 14. key scan control (ire = 0: key scan interrupt (irq) generation disabled, kf1/0 = 00: key scan set to 32 cycles) 15. port control (pt2/1/0 = 000: port2/1/0 output = gnd level)
hd66724/hd66725 56 ram data initialization: 1. ddram all addresses are initialized to 20h by the clear display instruction after the reset is canceled. 2. cgram/segram this is not automatically initialized by reset input but must be initialized by software while display is off (d = 0) output pin initialization: 1. lcd driver output pins (seg/com): outputs gnd level 2. booster output pins (vlout): outputs gnd level 3. oscillator output pin (osc2): outputs oscillation signal 4. key strobe pins (kst0 to kst3): kst0 outputs gnd level. kst1 to kst3 output v cc level. 5. key scan interrupt pin (irq*): outputs v cc level 6. general output port (port0?ort2): outputs gnd level
hd66724/hd66725 57 serial data transfer setting the im1 and im2 pins (interface mode pins) to the gnd level allows standard clock-synchronized serial data transfer, using the chip select line (cs*), serial data line (sda), and serial transfer clock line (scl). for a serial interface, the im0/id pin function uses an id pin. the hd66724/hd66725 initiate serial data transfer by transferring the start byte at the falling edge of cs* input. they end serial data transfer at the rising edge of cs* input. the hd66724/hd66725 are selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit device identification code assigned to the hd66724/hd66725. the hd66724/hd66725, when selected, receive the subsequent data string. the least significant bit of the identification code can be determined by the id pin. the five upper bits must be 01110. two different chip addresses must be assigned to a single hd66724/hd66725 because the seventh bit of the start byte is used as a register select bit (rs): that is, when rs = 0, an instruction can be issued or key scan data can be read, and when rs = 1, the data can be written to or read from ram. read or write is selected according to the eighth bit of the start byte (r/w bit) as shown in table 33. after receiving the start byte, the hd66724/hd66725 receive or transmit the subsequent data byte-by-byte. the data is transferred with the msb first. to transfer the data consecutively, note that only the display- clear instruction requires a longer execution time than the others (table 32). two bytes of the ram read data after the start byte are invalid. the hd66724/hd66725 start to read the correct ram data from the third byte. write a dummy instruction ("00h") before reading the key scan data. table 33 start byte format transfer bit s 1 2 3 4 5 6 7 8 start byte format transfer start device id code rs r/w 011 10id note: id bit is selected by the im0/id pin. table 34 rs and r/w bit function of clock-synchronized serial interface data rs r/w function 0 0 writes instruction 0 1 reads key scan data 1 0 writes ram data 1 1 reads ram data
hd66724/hd66725 58 a) basic data-transfer timing through clock-synchronized serial bus interface start byte instruction, ram data, key scan data 12345678910111213141516 db 7 db 6 db 5 db 4 r/w device id code scl (input) sda (input/ output) cs* (input) rs db 3 db 2 db 1 db 0 transfer start transfer end msb lsb rs r/w "0" "1" "1" "1" id "0" start byte instruction 1 execution time scl (input) sda (input/ output) b) consecutive data-transfer timing through clock-synchronized serial bus interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 instruction 1 instruction 2 20 21 22 23 24 25 26 27 28 29 30 31 32 instruction 2 execution time instruction 3 start end when instruction 1 is a clear display instruction, adjust the transfer rate so that the 8th bit of instruction 2 is transferred after execution of the clear display instruction. cs* (input) note: start byte rs = "1", r/w = "1" scl (input) sda (input/ output) c) ram data read-transfer timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 dummy read 1 dummy read 2 20 21 22 23 24 25 26 27 28 29 30 31 32 ram data read 1 start end two bytes of ram read data after the start byte are invalid. the hd66724/hd66725 start to read correct ram data from the third byte. cs* (input) note: figure 25 clock-synchronized serial interface timing sequence
hd66724/hd66725 59 key scan control the key matrix scanner senses and holds the key states at each rising edge of key strobe signals (kst) that are output by the hd66724/hd66725. the key strobe signals are output as time-multiplexed signals from kst0 to kst3. after passing through the key matrix, these strobe signals are used to sample the key state of eight inputs kin0 to kin7, enabling up to 32 keys to be scanned. the states of inputs kin0 to kin7 are sampled by key strobe signal kst0 and latched into the scan0 register. similarly, the data sampled by strobe signals kst1 to kst3 is latched into the scan1 to scan3 registers, respectively. key pressing is stored as 1 in these registers. the generation cycle and pulse width of the key strobe signals depend on the operating frequency (oscillation frequency) of the hd66724/hd66725 and the key scan cycle determined by the kf0 and kf1 bits. for example, when the operating frequency is 32 khz and kf0 and kf1 are both 10, the generation cycle is 4.0 ms and the pulse width is 1.0 ms. when the operating frequency (oscillation frequency) is changed, the above generation cycle and the pulse width are changed in inverse proportion. in order to compensate for the mechanical features of the keys, such as chattering and noise and for the key-strobe generation cycle and the pulse width of the hd66724/hd66725, software should read the scanned data two to three times in succession to obtain valid data. multiple keypress combinations should also be processed in the software. up to three keys can be pressed simultaneously. note, however, that if the third key is pressed on the intersection between the rows and columns of the first two keys pressed, incorrect data will be sampled. for three-key input, the third key must be on a separate column or row. the input pins kin0 to kin7 are pulled up to v cc with internal mos transistors (see the electrical characteristics section). external resistors may also be required to further pull the voltages up when the internal pull-ups are insufficient for the desired noise margins or for a large key matrix. scan0 scan1 scan2 scan3 d 03 d 02 d 01 d 00 kin3 kin2 kin1 kin0 (kst0 -) (kst1 -) (kst2 -) (kst3 -) d 13 d 12 d 11 d 10 d 23 d 22 d 21 d 20 d 33 d 32 d 31 d 30 d 04 kin4 d 14 d 24 d 34 d 05 kin5 d 15 d 25 d 35 d 06 kin6 d 16 d 26 d 36 d 07 kin7 d 17 d 27 d 37 ksd7 ksd6 ksd5 ksd4 ksd3 ksd2 ksd1 ksd0 figure 26 key scan register configuration
hd66724/hd66725 60 table 35 key scan cycles for each operating frequency kf1 kf0 key scan pulse width key scan cycle 0 0 0.25 ms 1.0 ms (32 clock cycles) 0 1 0.5 ms 2.0 ms (64 clock cycles) 1 0 1.0 ms 4.0 ms (128 clock cycles) 1 1 2.0 ms 8.0 ms (256 clock cycles) note: the data is a value obtained when the oscillation frequency (fosc) is 32 khz. the value depends on the oscillation frequency. 4.0 ms 1.0 ms kst0 kst1 kst2 kst3 key scan cycle figure 27 key strobe output timing (kf1/0 = 10, fcp/fosc = 32 khz) key matrix detail key strobe kin7 kin6 kin5 kin4 kin3 kin2 kin1 kin0 kst0 kst1 kst2 kst3 d 32 d 22 d 12 d 02 d 33 d 23 d 13 d 03 d 30 d 20 d 10 d 00 d 31 d 21 d 11 d 01 d 34 d 24 d 14 d 04 d 35 d 25 d 15 d 05 d 36 d 26 d 16 d 06 d 37 d 27 d 17 d 07 hd66724 hd66725 key state fetch figure 28 key scan configuration
hd66724/hd66725 61 the key scan data can be read by an mpu via a serial interface. first, a start byte should be transferred. after the hd66724/hd66725 have received the start byte, the mpu reads scan data ksd7 to ksd0 from the scan0 register starting from the msb. similarly, the mpu reads the data from scan1, scan2 and scan3 in that order. after reading scan3, the mpu starts reading at scan0 again. the hd66724/hd66725 may be read out while they are latching scan data and are thus unstable. consequently, they should also be reconfirmed with software if required. write a dummy instruction ("00h") before reading the key scan data. b) consecutive scan data read timing a) scan data read timing through clock-synchronized serial bus interface 12345678910111213141516 0 1 011 1 0id start byte device id code scl (input) sda (input/ output) cs* (input) wait start byte scl (input) sda (input/ output) scan0 data scan1 data scan2 data scan3 data scan0 data wait wait wait scan0 data transmission ksd7 ksd6 ksd5 ksd4 ksd3 ksd2 ksd1 ksd0 r/w rs transfer start transfer end figure 29 scan data serial transfer timing
hd66724/hd66725 62 key scan interrupt (wake-up function) if the interrupt enable bit (ire) is set to 1, the hd66724/hd66725 send an interrupt signal to the mpu on detecting that a key has been pressed in the key scan circuit by setting the irq* output pin to a low level. an interrupt signal can be generated by pressing any key in a 32-key matrix. the interrupt level continues to be output during the key scan cycle during which the key is being pressed. normal key scanning is performed and interrupts can occur in the hd66724/hd66725 sleep mode (slp = 1). accordingly, power consumption can be minimized in the sleep mode, by triggering the mpu to read key states via the interrupt which is generated only when the hd66724/hd66725 detect a key input. for details, refer to the sleep mode section. on the other hand, normal key scanning and the internal operating clock stop in the standby mode (stb = 1). during this period, the kst0 output is kept low, so the hd66724/hd66725 can always monitor eight key inputs (kin0-kin7) connected to kst0 when rs = gnd. therefore, if any of the eight keys is pressed, an interrupt occurs. when rs = vcc, all outputs kst0 to kst3 are kept low, so the hd66724/hd66725 can always monitor 32 key inputs. if any of 32 keys is pressed, an interrupt occurs. accordingly, power consumption can further be minimized in the standby mode, where the whole system is inactive, by triggering the mpu via the interrupt which is generated only when the hd66724/hd66725 detect a key input from the above keys. for details, refer to the standby mode section. the irq* output pin is pulled up to the v cc with an internal mos resistor of approximately 50 k w . additional external resistors may be required to obtain stronger pull-ups. interrupts may occur if noise occurs in kin0-kin7 input during key scanning. interrupts must be inhibited if not needed by setting the interrupt enable bit (ire) to 0. irq * interrupt generated hd66724 hd66725 irq * v cc mpu figure 30 interrupt generation
hd66724/hd66725 63 standby mode mask interrupts (ire = 0) wait 10 ms or longer (mpu) start r-c oscillator (hd66724/5) clear standby mode (stb = 0) turn off lcd power (amp = 0) set standby mode (stb = 1) generate interrupt (hd66724/5 read key-scanned data enable interrupts (ire = 1) turn off lcd power (amp = 0) set sleep mode (slp = 1) key input (key ? hd66724/5) generate interrupt (hd66724/5 ? mpu) sleep mode mask interrupts (ire = 0) read key-scanned data enable interrupts (ire = 1) ? hd66724/5) key input (key ? mpu) figure 31 key scan interrupt processing flow in sleep and standby modes
hd66724/hd66725 64 parallel data transfer 8-bit interface setting the im2/1/0 (interface mode) to the gnd/v cc /gnd level allows 68-system 8-bit parallel data transfer. a direct interface using the 8-bit e-clock-synchronized bus or an interface via the i/o bus can be established. setting the im2/1/0 to the v cc /v cc /gnd level allows 80-system 8-bit parallel data transfer. when the number of buses or mounting area is limited, use a 4-bit bus interface or serial data transfer. using a parallel bus interface disables the key scan function. to prevent this, use a clock-synchronized serial interface. c0 c1 c2 a0?7 e rs r/w db0?b7 h8/325 hd66724 hd66725 8 *interface via i/o port figure 32 interface to 8-bit microcomputer 4-bit interface setting the im2/1/0 (interface mode) to the gnd/v cc /v cc level allows 68-system 4-bit parallel data transfer using pins db7/kin7-db4/kin4. setting the im2/1/0 to the v cc /v cc /v cc level allows 80-system 4-bit parallel data transfer. 8-bit instructions and ram data are divided into four upper/lower bits and transfer starts from the upper four bits. using a parallel bus interface disables the key scan function. to prevent this, use a clock-synchronized serial interface. note: transfer synchronization function for a 4-bit bus interface the hd66724/hd66725 support transfer synchronization function which resets the upper/lower counter to count upper/lower four-bit data transfer in the 4-bit bus interface. noise causing transfer mismatch between the four upper and lower bits can be corrected by a reset triggered by consecutively writing a 0000 instruction four times. the next transfer starts from the upper four bits. executing synchronization function periodically can recover any runaway in the display system.
hd66724/hd66725 65 0000 0000 0000 0000 rs r/w e db7 -db4 (1) (2) (3) (4) upper/ lower upper lower (4-bit transfer synchronization) figure 33 4-bit transfer synchronization
hd66724/hd66725 66 oscillator circuit the hd66724/hd66725 can either be supplied with operating pulses externally (external clock mode), oscillate using an internal cr oscillator with an external oscillator-resistor (external resistor oscillation mode), or oscillate using an internal oscillator-resistor (internal resistor oscillation mode). internal oscillator-resistors fluctuate by 30% depending on products. avoid frame frequency fluctuations as these affect video quality. to prevent these, use an external resistor. osc1 osc1 osc2 clock (32 khz) rf the oscillator frequency can be adjusted by oscillator resistor (rf). if rf is increased or power supply voltage is decreased, the oscillator frequency decreases. for the relationship between rf resistor value and oscillation frequency, see the electric characteristics footnote section. hd66724 hd66725 1) external clock mode 2) external resistor oscillation mode 3) internal resistor oscillation mode hd66724 hd66725 osc1 osc2 rf 0 (= 650 k /typ.) hd66724 hd66725 rf 1 (= 350 k /typ.) rf 2 (= 100 k /typ.) r1 r2 r3 note that the internal resistors rf0, rf1, and rf2 fluctuate by 30% depending on products. i) r1-osc2 short-circuiting rf = rf 0 = 650 k (typ.) ii) r1-r2 short-circuiting, r3-osc2 short-circuiting rf = rf 0 + rf 2 = 750 k (typ.) iii) r2-osc2 short-circuiting rf = rf 0 + rf 1 = 800 k (typ.) iv) r3-osc2 short-circuiting rf = rf 0 + rf 1 + rf 2 = 900 k (typ.) figure 34 oscillator circuits table 36 multiplexing duty ratio and lcd frame frequency (fosc = 32 khz) item segment mode (nl2/1/0 = 000) 1-line display (nl2/1/0 = 001) 2-line display (nl2/1/0 = 010) 3-line display (nl2/1/0 = 011) multiplexing duty ratio 1/2 1/10 1/18 1/26 optimum drive bias (recommended value) 1/2 1/4 1/5 1/6 frame frequency 80 hz 80 hz 74 hz 77 hz
hd66724/hd66725 67 1 2 3 4 25 26 1 2 3 25 26 v1 v2 v5 gnd coms1 v2 v5 gnd com1 1 frame 1 frame v1 v2 v5 gnd com24 v1 v2 v5 gnd coms2 v1 figure 35 lcd drive output waveform (3-line display with 1/26 multiplexing duty ratio)
hd66724/hd66725 68 power supply for liquid crystal display drive when external power supply and internal operational amplifiers are used to supply lcd drive voltage directly from the external power supply without using the internal booster, circuits should be connected as shown in figure 36. here, contrast can be adjusted through the ct bits of the contrast control instruction. the hd66724/hd66725 incorporate a voltage-follower operational amplifier for each v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. thus, potential differences between v lcd and v1 and between v5 and gnd must be 0.1 v or higher. note that the opoff pin must be grounded when using the operational amplifiers. place a capacitor of about 0.1 m f to 0.5 m f between each internal operational amplifier v1out to v5out output and gnd and stabilize the output level of the operational amplifier.
hd66724/hd66725 69 c1+ v lcd v lcd vr r 0 r r r - + - + - + - + - + gnd booster opoff=gnd r hd66724/5 v1out + v2out v3out v4out v5out + + + + lcd driver seg1 to seg72 (96) com1 to com24 coms1 to coms2 v1 v3 v4 v2 v5 gnd vci c1- c2+ c2- vlout 0.1 f to 0.5 f gnd figure 36 external power supply circuit for lcd drive voltage generation when an internal booster and internal operational amplifiers are used to supply lcd drive voltage using the internal booster, circuits should be connected as shown in figure 37. here, contrast can be adjusted through the ct bits of the contrast control instruction. temperature can be compensated either through the ct bits or by controlling the reference voltage for the booster (vci pin) using a thermistor. note that vci is both a reference voltage and power supply for the booster. the reference voltage must therefore be adjusted using an emitter-follower or a similar element so that sufficient current can be supplied. in this case, vci must be equal to or smaller than the v cc level. the hd66724/hd66725 incorporate a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different liquid-crystal drive voltages. thus, the potential differences between v lcd and v1 and between v5 and gnd must be 0.1 v or higher. note that the opoff pin must be grounded when using the operational amplifiers. place a capacitor of about 0.1 m f to 0.5 m f between each internal operational amplifier v1out to v5out output and gnd and stabilize the output level of the operational amplifier.
hd66724/hd66725 70 notes: 1. the reference voltage input (vci) must be adjusted so that the output voltage after boosting will not exceed the absolute maximum rating for the liquid-crystal power supply voltage (7 v). particularly, vci must be 2.3 v or less for triple boosting. 2. vci is both a reference voltage and power supply for the booster; connect it to vcc directly or combine it with a transistor so that sufficient current can be obtained. 3. vci must be smaller than vcc. 4. when using up to the double booster, no capacitors are required between c2+ and c2? 5. polarized capacitors must be connected correctly. 6. circuits for temperature compensation should be based on the sample circuit below. v lcd v lcd vr r 0 r r r - + - + - + - + - + gnd c1+ c1- vci + 0.47 f to 1 f 0.47 f to 1 f 0.47 f to 1 f vlout gnd + c2+ c2- + booster opoff=gnd r hd66724/5 v1out + v2out v3out v4out v5out + + + + lcd driver seg1 to seg72 (96) com1 to com24 coms1 to coms2 v1 v3 v4 v2 v5 gnd 0.1 f to 0.5 f gnd vci figure 37 internal booster circuit for lcd drive voltage generation vcc thermistor gnd tr vcc vci hd66724/5 figure 38 external power supply circuit for lcd drive voltage generation
hd66724/hd66725 71 when an internal booster and external bleeder-resistors are used when internal operational amplifiers cannot fully drive the lcd panel used, v1 to v5 voltages can be supplied through external bleeder-resistors (figure 39). here, the opoff pin must be set to the v cc level to turn off the internal operational amplifiers. since the internal contrast adjuster is disabled, contrast must be adjusted externally. connection of external bleeder-resistors can specify a given bias value from 1/2 to 1/6. figure 39 shows connection for 1/6-bias drive voltage generation. double- and triple-boosters can be used as they are. c1+ c1- vci vlout + vlcd v1out v2out v3out v4out v5out - + - + - + - + - + gnd booster gnd + 0.47 f to 1 f 0.47 f to 1 f hd66724/5 opoff = vcc vr r 2r r r r c2+ c2- + 0.47 f to 1 f vci gnd seg1 to seg72 (96) com1 to com24 coms1 to coms2 v1 v2 v3 v4 v5 gnd lcd driver notes: 1. resistance of each external bleeder resistor should be 4.7 k to 25 k . 2. the bias current value for driving lcds can be varied by adjusting the resistance (2r) between the v3out and v4out pins. 3. the internal contrast adjuster is disabled; contrast must be adjusted either by controlling the external variable resistor between vlcd and v1 for the booster. 4. vci is both a reference voltage and power supply for the booster; connect it to vcc directly or combine it with a transistor so that sufficient current can be obtained. 5. vci must be smaller than vcc. figure 39 circuit using external bleeder-resistors
hd66724/hd66725 72 contrast adjuster contrast for an lcd can be adjusted by varying the liquid-crystal drive voltage (potential difference between v lcd and v1) through the ct bits of the contrast control instruction (electron volume function). see figure 40 and table 37. the value of a variable resistor (vr) can be adjusted within a range from 0.1 x r through 3.2 x r, where r is a reference resistance obtained by dividing the total resistance between v lcd and v1. the hd66724/hd66725 incorporate a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different liquid-crystal drive voltages. thus, ct4-0 bits must be adjusted so that the potential differences between v lcd and v1 and between v5 and gnd are 0.1 v or higher when liquid-crystal drives. v lcd vr r r r 0 r r - + - + - + - + - + gnd hd66724/5 ct v1 v2 v3 v4 v5 gnd figure 40 contrast adjuster
hd66724/hd66725 73 table 37 contrast-adjust bits (ct) and variable resistor values 0 ct3 0 ct2 0 ct1 0 ct0 3.2 x r ct set value 00 0 1 3.1 x r 00 1 0 3.0 x r 00 11 2.9 x r 0 1 00 2.8 x r 0 1 0 1 2.7 x r 0 11 0 2.6 x r 0 11 1 2.5 x r 0 ct4 0 0 0 0 0 0 0 1 00 1 2.3 x r 0 1 0 1 0 2.2 x r 0 1 0 1 2.1 x r 0 1 1 00 2.0 x r 0 1 1 0 1 1.9 x r 0 1 11 0 1.8 x r 0 1 11 1 1.7 x r 0 0 000 1.6 x r 1 000 1 1.5 x r 1 0 0 1 0 1.4 x r 1 0 0 11 1.3 x r 1 0 1 00 1.2 x r 1 0 1 0 1 1.1 x r 1 0 11 0 1.0 x r 1 0 11 1 0.9 x r 1 1 000 0.8 x r 1 1 00 1 0.7 x r 1 1 0 1 0 0.6 x r 1 1 0 11 0.5 x r 1 1 1 00 0.4 x r 1 1 1 0 1 0.3 x r 1 1 11 0 0.2 x r 1 1 11 1 0.1 x r 1 1 00 0 2.4 x r 0 1 variable resistor value (vr) potential difference between v1 and gnd display color (small) (light) (large) (deep)
hd66724/hd66725 74 table 38 contrast adjustment per bias drive voltage 6 x r + vr 6 x r x (v lcd - gnd) 0.652 x (v lcd -gnd) v dr 0.984 x (v lcd -gnd) 3 0.1[v] 3 0.1[v] 6 x r + vr vr x (v lcd -gnd) 6 x r + vr r x (v lcd -gnd) 5 x r + vr 5 x r x (v lcd - gnd) 0.610 x (v lcd -gnd ) v dr 0.980 x (v lcd -gnd) 3 0.1[v] 3 0.1[v] 5 x r + vr vr x (v lcd -gnd ) 5 x r + vr r x (v lcd -gnd ) 4 x r + vr 4 x r x (v lcd - gnd) 0.556 x (v lcd -gnd) v dr 0.976 x (v lcd -gnd) 3 0.1[v] 3 0.1[v] 4 x r + vr vr x (v lcd -gnd) 4 x r + vr r x (v lcd -gnd) 4.5 x r + vr 4.5 x r x (v lcd - gnd) 0.556 x (v lcd -gnd) v dr 0.978 x (v lcd -gnd) 3 0.1[v] 3 0.1[v] 4.5 x r + vr vr x (v lcd -gnd) 4.5 x r + vr r x (v lcd -gnd) 5.5 x r + vr 5.5 x r x (v lcd - gnd) 0.632 x (v lcd -gnd) v dr 0.982 x (v lcd -gnd) 3 0.1[v] 3 0.1[v] 5.5 x r + vr vr x (v lcd -gnd) 5.5 x r + vr r x (v lcd -gnd) 6.5 x r + vr 6.5 x r x (v lcd - gnd) 0.670 x (v lcd -gnd) v dr 0.985 x (v lcd -gnd) 3 0.1[v] 3 0.1[v] vr x (v lcd -gnd) 6.5 x r + vr r x (v lcd -gnd) 6.5 x r + vr bias lcd drive voltage: v dr contrast adjustment range 1/6.5 bias drive 1/6 bias drive 1/5.5 bias drive 1/5 bias drive 1/4.5 bias drive 1/4 bias drive - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : :
hd66724/hd66725 75 liquid crystal display drive bias selector circuit an optimum liquid crystal display bias value can be selected using bs2-0 bits, according to the liquid crystal drive duty ratio setting (nl2-0 bits). liquid crystal display drive duty ratio and bias value can be displayed while switching software applications to match the lcd panel display status. the optimum bias value calculated using the following expression is an ideal value where the optimum contrast is obtained. driving by using a lower value than the optimum bias value provides lower contrast and lower liquid crystal display voltage (potential difference between v1 and gnd). when the liquid crystal display voltage is insufficient even if a triple booster is used or output voltage is lowered because the battery life has been reached, the display can be made easier to see by lowering the liquid crystal bias. the liquid crystal display can be adjusted by using the contrast adjustment register (ct4-0 bits) and selecting the booster output level (bt1/0 bits). n + 1 1 optimum bias value for 1/n duty ratio drive voltage = table 39 optimum drive bias values lcd drive duty ratio (nl2-0 set value) 1/26 duty ratio (nl2-0 = 011) 1/18 duty ratio (nl2-0 = 010) 1/10 duty ratio (nl2-0 = 001) 1/2 duty ratio (nl2-0 = 000) optimum drive bias value (bs2-0 set value) 1/6 bias (bs2-0 = 001) 1/5 bias (bs2-0 = 011) 1/4 bias (bs2-0 = 101) 1/4 bias (bs2-0 = 101)
hd66724/hd66725 76 v r v1 v2 v3 v4 v5 r r 2.5r r r v1 v2 v3,v4 v5 gnd r r r r i) 1 / 6.5 bias (bs2-0 = 000) vi) 1 / 4 bias (bs2-0 = 101) gnd v r v lcd v lcd v r v1 v2 v3 v4 v5 r r 2r r r ii) 1 / 6 bias (bs2-0 = 001) v lcd v r v1 v2 v3 v4 v5 r r 1.5r r r iii) 1 / 5.5 bias (bs2-0 = 010) v lcd v r v1 v2 v3 v4 v5 r r r r r iv) 1 / 5 bias (bs2-0 = 011) v lcd v r gnd v1 v2 v3 v4 v5 r r 0.5r r r v) 1 / 4.5 bias (bs2-0 = 100) v lcd gnd gnd gnd gnd gnd gnd gnd gnd gnd note: r=reference resistor figure 41 liquid crystal display drive bias circuit
hd66724/hd66725 77 lcd panel interface the hd66724/hd66725 have a function for changing the common driver/segment driver output shift direction using the cms bit and sgs bit to meet the chip mounting positions of the hd66724/hd66725. this is to facilitate the interface wiring to the lcd panel with cog or tcp installed. wiring for 3-line display (1/26 duty ratio) figure 42 3-line display pattern wiring
hd66724/hd66725 78 wiring for 2-line display (1/18 duty ratio) figure 43 2-line display pattern wiring
hd66724/hd66725 79 cgrom bank switching function the hd66724/hd66725 incorporate two pages of cgrom. switching the memory bank using the cgrom bank switching bit (rom) can display a total of 432 font patterns. multinational fonts, special symbols, and icons can be displayed. note that the number of fonts simultaneously displayed is cgrom: 240 + cgram: 16 when memory bank 0 is selected, and cgrom: 192 + cgram: 64 when memory bank 1 is selected. font displays for cgram (1) to (16) are used in common with memory bank 0 and memory bank 1. table 40 cgrom bank switching character code memory bank 0 (rom = 0) memory bank 1 (rom = 1) "00"h to "0f"h cgram (1) to (16) cgram (1) to (16) "10"h to "1f"h cgrom (1) to (16) cgram (17) to (32) "20"h to "2f"h cgrom (17) to (32) cgrom (241) to (256) "30"h to "3f"h cgrom (33) to (48) cgrom (257) to (272) "40"h to "4f"h cgrom (49) to (64) cgrom (273) to (288) "50"h to "5f"h cgrom (65) to (80) cgrom (289) to (304) "60"h to "6f"h cgrom (81) to (96) cgrom (305) to (320) "70"h to "7f"h cgrom (97) to (112) cgrom (321) to (336) "80"h to "8f"h cgrom (113) to (128) cgram (33) to (48) "90"h to "9f"h cgrom (129) to (144) cgram (49) to (64) "a0"h to "af"h cgrom (145) to (160) cgrom (337) to (352) "b0"h to "bf"h cgrom (161) to (176) cgrom (353) to (368) "c0"h to "cf"h cgrom (177) to (192) cgrom (369) to (384) "d0"h to "df"h cgrom (193) to (208) cgrom (385) to (400) "e0"h to "ef"h cgrom (209) to (224) cgrom (401) to (416) "f0"h to "ff"h cgrom (225) to (240) cgrom (417) to (432)
hd66724/hd66725 80 graphics display function the hd66724/hd66725 have a character display mode (gr = 0) where cgram or cgrom is used to display font patterns, and a graphics display mode (gr = 1) where bit pattern data is set to cgram to display given patterns. in the character display mode, an lcd panel display can easily be provided by sending byte-per-character character codes to ddram, but any pattern not set to cgrom or cgram cannot be displayed. in the graphics display mode, all bit pattern data to be displayed must be sent although any pattern can be displayed. the hd66724/hd66725 support both of these modes which can easily be switched using the gr bit. in the graphics display mode, kanji characters, special symbols, and graphic icons can be displayed. in the hd66724, up to a 72 x 26-dot display is allowed using cgram and segram. thus, for a 12 x 12-dot kanji font, up to a 2-line x 6-character kanji display is allowed. in the hd66725, up to a 96 x 26-dot display is allowed, and up to a 2-line x 8-character kanji display is allowed for a 12 x 12-dot kanji font. kanji kanji figure 44 kanji display in graphics display mode
hd66724/hd66725 81 vertical smooth scroll the hd66724/hd66725 can scroll vertically in units of raster-rows. in character display mode (gr = 0), this is achieved by writing character codes into a ddram area that is not being used for display. in other words, since ddram corresponds to a 5-line 16-character display, two lines can be used to achieve continuous smooth vertical scroll even in a 3-line display. here, after the fifth line is displayed, the first line is displayed again. in the graphics display mode (gr = 1), a 96 x 32-dot area is assigned as cgram. thus a non-display area other than the 72 x 24-dot display area can be used to provide consecutive, smooth scroll display. segment (mark) display is system-fixed and the scroll function cannot be used. specifically, this function is controlled by incrementing or decrementing the value in the display-start line bits (sl2 to sl0) and display-start raster-row bits (sn2/1/0) by 1. for example, to smoothly scroll up, first set line bits sn2 to sn0 to 000, and increment sl2 to sl0 by 1 from 000 to 111 to scroll seven raster- rows. then increment line bits sn2 to sn0 to 001, and again increment sl2 to sl0 by 1 from 000 to 111. to start displaying and scrolling from the first raster-row of the second line, update the first line of ddram or cgram data as desired during its non-display period.
hd66724/hd66725 82 figure 45 vertical smooth scroll
hd66724/hd66725 83 setting instructions (character display mode: gr = 0, 3-line display: nl2-0 = 011) db7 db6 db5 db4 db3 db2 db1 db0 r/w rs 00010 cpu wait cpu wait cpu wait 0 0 1 0 0001 00 0 010 0001010 0001 1 0 0 010 0001 0 0 1 010 0001 1 0 1 010 00010 0 1 1 0 0001 00 0 010 0001 00 0 010 cpu wait cpu wait cpu wait 0001 1 0 0 010 0001 0 0 1 010 0001 1 0 1 010 00010 1 0 0001 00 0 010 0001 00 0 010 1 0 cpu wait cpu wait 0001 1 0 0 010 0001 0 0 1 010 0 0 0 0 0 0 *1st to 3rd lines are being displayed scroll up 2 raster-rows (3rd raster-row of 1st line displayed at the top) scroll up 4 raster-rows (5th raster-row of 1st line displayed at the top) scroll up 6 raster-rows (7th raster-row of 1st line displayed at the top) (1st raster-row of 2nd line displayed at the top) sn2 ?sn0 = 001 sl2 ?sl0 = 000 sn2 ?sn0 = 010 sl2 ?sl0 = 000 *while 1st and 5th lines are not displayed, 2nd to 4th lines are being displayed scroll up 10 raster-rows (3rd raster-row of 2nd line displayed at the top) scroll up 12 raster-rows (5th raster-row of 2nd line displayed at the top) scroll up 14 raster-rows (7th raster-row of 2nd line displayed at the top) (1st raster-row of 3rd line displayed at the top) *while 1st and 2nd lines are not displayed, 3rd to 5th lines are being displayed scroll up 18 raster-rows (3rd raster-row of 3rd line displayed at the top) scroll up 20 raster-rows (5th raster-row of 3rd line displayed at the top) scroll up display set initial character codes of 5 lines to all ddram addresses sn2 ?sn0 = 000 sl2 ?sl0 = 000 (1st raster-row of 1st line displayed at the top) update 1st-line (address 00h to 0fh) character codes in ddram update 2nd-line (address 10h to 1fh) character codes in ddram figure46 setting instructions for vertical smooth scroll (character display mode)
hd66724/hd66725 84 setting instructions (graphics display mode: gr = 1, 3-line display: nl2-0 = 011) db7 db6 db5 db4 db3 db2 db1 db0 r/w rs 00010 cpu wait cpu wait cpu wait 00 1 0 0001010 0001010 0001 1 0 0 010 0001 0 0 1 010 0001 1 0 1 010 00010 0 1 1 0 0001 00 0 010 0001 00 0 010 cpu wait cpu wait cpu wait 0001 1 0 0 010 0001 0 0 1 010 0001 1 0 1 010 00010 1 0 0001 00 0 010 0001 00 0 010 1 0 cpu wait cpu wait 0001 1 0 0 010 0001 0 0 1 010 0 0 0 scroll up display (1st raster-row of 1st line displayed at the top) sn2 ?sn0 = 000 sl2 ?sl0 = 000 sn2 ?sn0 = 001 sl2 ?sl0 = 000 sn2 ?sn0 = 010 sl2 ?sl0 = 000 set 72 x 32-dot initial display data to cgram *1st to 3rd lines are being displayed scroll up 2 raster-rows (3rd raster-row of 1st line displayed at the top) scroll up 4 raster-rows (5th raster-row of 1st line displayed at the top) scroll up 6 raster-rows (7th raster-row of 1st line displayed at the top) (1st raster-row of 2nd line displayed at the top) update 1st-line (address 000h to 047h) display data in cgram *2nd to 4th lines are being displayed scroll up 10 raster-rows (3rd raster-row of 2nd line displayed at the top) scroll up 12 raster-rows (5th raster-row of 2nd line displayed at the top) scroll up 14 raster-rows (7th raster-row of 2nd line displayed at the top) (1st raster-row of 3rd line displayed at the top) update 2nd-line (address 100h to 147h) display data in cgram *3rd, 4th, and 1st lines are being displayed scroll up 18 raster-rows (3rd raster-row of 3rd line displayed at the top) scroll up 20 raster-rows (5th raster-row of 3rd line displayed at the top) 000 figure 47 setting instructions for vertical smooth scroll (graphics display mode)
hd66724/hd66725 85 horizontal smooth scroll the hd66724/hd66725 perform the horizontal smooth scroll in 3-dot units. in the character display mode (gr = 0), an area of 16 characters x 5 lines is assigned as ddram. in the graphics display mode (gr = 1), a 96 x 32-dot area is assigned as cgram. these non-display areas are used to provide a horizontal smooth scroll display. when the hd66725 displays 16 characters or 96 dots, there are no non-display areas and horizontal scrolling cannot be done. display lines for horizontal scroll can be separately specified using the horizontal scroll bits (se4-1), allowing a scroll of the whole display or specified lines. horizontal scroll dots can be specified using the horizontal scroll dot bits (sq2-0), allowing up to a 21-dot scroll at a time. for further scrolls, data in the ddram or cgram must be overwritten. figure 48 horizontal smooth scroll display
hd66724/hd66725 86 db7 db6 db5 db4 db3 db2 db1 db0 rs r/w 0010 00 cpu wait cpu wait cpu wait cpu wait 2 3 4 8 11 1 0 000 1 01 1 0 1 1 1 00 01 01 0 100 00 01 10 0 100 00 01 1 1 0 100 cpu wait 00 01 0 0 0 100 cpu wait 10 00 01 01 0 100 9 scroll enabled (3rd line only) 3-dot shift to the left on the 3rd line 6-dot shift to the left on the 3rd line 9-dot shift to the left on the 3rd line 21-dot shift to the left on the 3rd line character display mode: character codes on the 3rd line in ddram are shifted 4 characters to the left and data is overwritten graphics display mode: display data on the 3rd line in cgram is shifted 24 dots to the left and data is overwritten 3rd line is not shifted 3rd line is shifted 3 dots to the left figure 49 smooth scroll to the left
hd66724/hd66725 87 double-height display the hd66724/hd66725 can double the height of any desired line from the first to third lines. a line can be selected by the dl3 to dl1 bits as listed in table 41. all the standard font characters stored in the cgrom and cgram can be doubled in height, allowing easy recognition. note that there should be no space between the lines for double-height display (figure 50). table 41 double-height display specifications dl3 dl2 dl1 2-line display (nl2-0 = 010) 3-line display (nl2-0 = 011) 0 0 0 1st & 2nd lines: normal 1st to 3rd lines: normal 0 0 1 1st line: double-height 1st line: double-height, 2nd line: normal 0 1 0 disabled 2nd line: double-height, 1st line: normal 0 1 1 1st line: double-height disabled 1 0 0 1st & 2nd lines: normal disabled 1 0 1 1st line: double-height 1st line: double-height, 2nd line: normal 1 1 0 disabled 2nd line: double-height, 1st line: normal 1 1 1 1st line: double-height disabled
hd66724/hd66725 88 1st to 3rd lines: normal display dl3/2/1 = 010 (2nd line: double-height display) 1st line: normal display 2nd line: double-height display figure 50 double-height display blink mark display the hd66724/hd66725 have a grayscale display and blink display based on 144 (192) individual segments (marks). forty-eight (sixty-four) of these are for grayscale display and the remainder are for blink display. these 48 (64) segments can also control a grayscale display, providing simple grayscale on specific pictograms or marks. for example, the battery no charge alarm uses this dispay. the above display uses a curtailed frame grayscale system, and flicker may result in quick-response liquid crystal materials. tables 42 and 43 show the relationship between set data in segram and effective applied voltage during frame curtailing operation. the remaining 96 (128) segments are resposible for normal blinking and double-speed blinking. normal blinking (b & w) is achieved by repeatedly turning on each segment for 32 frames and turning it off for the next 32 frames. double-speed blinking (b & w) is achieved by repeatedly turning on each segment for 16 frames and turning it off for the next 16 frames, that is, double the speed of normal blinking.
hd66724/hd66725 89 table 42 relationship between segment driver output pin and segment display function (hd66724) when sgs = 0 when sgs = 1 segment output control seg1/72, seg4/69, seg7/66 seg10/63, seg13/60, seg16/57 seg19/54, seg22/51, seg25/48 seg28/45, seg31/42, seg34/39 seg37/36, seg40/33, seg43/30 seg46/27, seg49/24, seg52/21 seg55/18, seg58/15, seg61/12 seg64/9, seg67/6, seg70/3 seg72/1, seg69/4, seg66/7 seg63/10, seg60/13, seg57/16 seg54/19, seg51/22, seg48/25 seg45/28, seg42/31, seg39/34 seg36/37, seg33/40, seg30/43 seg27/46, seg24/49, seg21/52 seg18/55, seg15/58, seg12/61 seg9/64, seg6/67, seg3/70 grayscale segment display allowed output pins other than above output pins other than above segment blinking allowed table 43 relationship between segment driver output pin and segment display function (hd66725) when sgs = 0 when sgs = 1 segment output control seg1/96, seg4/93, seg7/90, seg10/87, seg13/84, seg16/81, seg19/78, seg22/75, seg25/72, seg28/69, seg31/66, seg34/63, seg37/60, seg40/57, seg43/54, seg46/51, seg49/48, seg52/45, seg55/42, seg58/39, seg61/36, seg64/33, seg67/30, seg70/27, seg73/24, seg74/21, seg79/18, seg82/15, seg85/12, seg88/9, seg91/6, seg94/3 seg96/1, seg93/4, seg90/7, seg87/10, seg84/13, seg81/16, seg78/19, seg75/22, seg72/25, seg69/28, seg66/31, seg63/34, seg60/37, seg57/40, seg54/43, seg51/46, seg48/49, seg45/52, seg42/55, seg39/58, seg36/61, seg33/64, seg30/67, seg27/70, seg24/73, seg21/76, seg18/79, seg15/82, seg12/85, seg9/88, seg6/91, seg3/94 grayscale segment display allowed output pins other than above output pins other than above segment blinking allowed
hd66724/hd66725 90 table 44 relationship between segram data and grayscale segment display (grayscale control segment driver) segram data setting effective applied voltage segram data setting effective applied voltage db3 db2 db1 db0 for coms1 segment db7 db6 db5 db4 for coms2 segment 0 0 0 0 0 (always unlit) 0 0 0 0 0 (always unlit) 0 0 0 1 1 (always lit) 0 0 0 1 1 (always lit) 0 0 1 0 0.34 (grayscale display) 0 0 1 0 0.34 (grayscale display) 0 0 1 1 0.38 (grayscale display) 0 0 1 1 0.38 (grayscale display) 0 1 0 0 0.41 (grayscale display) 0 1 0 0 0.41 (grayscale display) 0 1 0 1 0.44 (grayscale display) 0 1 0 1 0.44 (grayscale display) 0 1 1 0 0.47 (grayscale display) 0 1 1 0 0.47 (grayscale display) 0 1 1 1 0.50 (grayscale display) 0 1 1 1 0.50 (grayscale display) 1 0 0 0 (blink display) * 1 0 0 0 (blink display) * 1 0 0 1 0.53 (grayscale display) 1 0 0 1 0.53 (grayscale display) 1 0 1 0 0.56 (grayscale display) 1 0 1 0 0.56 (grayscale display) 1 0 1 1 0.59 (grayscale display) 1 0 1 1 0.59 (grayscale display) 1 1 0 0 0.63 (grayscale display) 1 1 0 0 0.63 (grayscale display) 1 1 0 1 0.66 (grayscale display) 1 1 0 1 0.66 (grayscale display) 1 1 1 0 0.69 (grayscale display) 1 1 1 0 0.69 (grayscale display) 1 1 1 1 0.72 (grayscale display) 1 1 1 1 0.72 (grayscale display) note: blinking is achieved by repeatedly turning on the segment for 32 frames and turning it off for the next 32 frames.
hd66724/hd66725 91 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 (on) (off) (blinking) grayscale control range effective applied voltage ratio segram set data figure 51 relationship between segram set data and effective applied voltage table 45 relationship between segram data and blinking control segment display (blinking control segment driver) segram data setting lcd display control for segram data setting lcd display control for db3 db2 db1 db0 coms1 segment db7 db6 db5 db4 coms2 segment 0* 1 * 1 0 0 (always unlit) 0 * 1 * 1 0 0 (always unlit) 0* 1 * 1 1 1 (always lit) 0 * 1 * 1 1 1 (always lit) 1* 1 * 1 0 blinking display * 2 1* 1 * 1 0 blinking display * 2 1* 1 * 1 1 double-speed blinking display * 3 1* 1 * 1 1 double-speed blinking display * 3 notes: 1. 0 or 1. 2. blinking is achieved by repeatedly turning on the segment for 32 frames and turning it off for the next 32 frames. 3. double-speed blinking is achieved by repeatedly turning on the segment for16 frames and turning it off for the next 16 frames.
hd66724/hd66725 92 alternates every 32 frames alternates every 16 frames figure 52 blinking control segment display line-cursor display the hd66724/hd66725 can assign a cursor attribute to an entire line corresponding to the address counter value by setting the lc bit to 1. one of three line-cursor modes can be selected: a black-white inverting cursor (b/w = 1), an underline cursor (c = 1), and a blink cursor (b = 1). the cycle for a blink cursor is 32 frames. these line-cursors are suitable for highlighting an index and/or marker, or for indicating an item in a menu with a cursor or an underline. table 46 address counter value and line-cursor address counter value (ac) selected line for line-cursor 00h to 0fh entire 1st line (16 characters) 10h to 1fh entire 2nd line (16 characters) 20h to 2fh entire 3rd line (16 characters) 30h to 3fh entire 4th line (16 characters) 40h to 4fh entire 5th line (16 characters)
hd66724/hd66725 93 normal display (lc = 0) figure 53 normal display black-white reversed cursor (lc = 1, b/w = 1) figure 54 black-white reversed cursor
hd66724/hd66725 94 underline cursor (lc = 1, c = 1) figure 55 underline cursor
hd66724/hd66725 95 blink cursor (lc = 1, b = 1) alternates every 32 frames figure 56 blink cursor
hd66724/hd66725 96 partial-display-on function the hd66724/hd66725 can program the liquid crystal display drive duty ratio setting (nl2-0 bits), liquid crystal display drive bias value selection (bs2-0 bits), boost output level selection (bt1/0 bit) and contrast adjustment (ct4-0 bits). in the three-line display mode (1/26 duty ratio), the hd66724/hd66725 can drive only one line in the center of the screen by combining these register functions and the centering display (cen bit) function. this is called partial-display-on. lowering the liquid crystal display drive duty ratio as required saves the liquid crystal display drive voltage, thus reducing internal current consumption. this is suitable for calendar or time display, which needs to be continuous in the system standby state with minimal current consumption. here, the non-displayed lines are constantly driven by the deselection level voltage, thus turning off the lcd for the lines. in general, lowering the liquid crystal display drive duty ratio decreases the optimum liquid crystal display drive voltage and liquid crystal display drive bias value. table 47 partial-display-on function item normal 3-line display partially-on display character display 1st to 3rd lines displayed only one line in the center of the screen segment display possible (144) possible (144) centering display not necessary (cen = 0) possible (cen = 1) lcd drive duty ratio 1/26 (nl2/1/0 = 011) 1/10 (nl2/1/0 = 001) possible lcd drive bias value (optimum) 1/6 (bs2-0 = 001) 1/4 (bs2-0 = 101) lcd drive voltage adjustable using bt1/0 and ct4-0 adjustable using bt1/0 and ct4-0 frame frequency (fosc = 32 khz) 77 hz 80 khz
hd66724/hd66725 97 figure 57 partial-on display (date and time indicated)
hd66724/hd66725 98 sleep mode setting the sleep mode bit (slp) to 1 puts the hd66724/hd66725 in the sleep mode, where the device stops all internal display operations except for key scan operations, thus reducing current consumption. specifically, lcd drive is completely halted. here, all the seg (seg1 to seg72 (96)) and com (com1 to com24, coms1/2) pins output the gnd level, resulting in no display. if the amp bit is set to 0 in the sleep mode, the lcd drive power supply can be turned off, reducing the total current consumption of the lcd module. the key scan circuit operates normally in the sleep mode, thus allowing normal key scan and key scan interrupt generation. for details, refer to the key scan control section and key scan interrupt (wake-up function) section. table 48 comparison of sleep mode and standby mode function sleep mode (slp = 1) standby mode (stb = 1) character display turned off turned off segment display turned off turned off r-c oscillation operates normally halted key scan can operate normally halted but irq* can be generated
hd66724/hd66725 99 standby mode setting the standby mode bit (stb) to 1 puts the hd66724/hd66725 in the standby mode, where the device stops completely, halting all internal operations including the r-c oscillator, thus further reducing current consumption compared to that in the sleep mode. specifically, character and segment displays, which are controlled by the multiplexing drive method, are completely halted. here, all the seg (seg1 to seg72 (96)) and com (com1 to com24, coms1/2) pins output the gnd level, resulting in no display. if the amp bit is set to 0 in the standby mode, the lcd drive power supply can be turned off. during the standby mode, no instructions can be accepted other than those for the start-oscillator instruction and the key scan interrupt generation enable instruction. to cancel the standby mode, issue the start oscillator instruction to stabilize r-c oscillation before setting the stb bit to 0. although key scan is halted in the standby mode, the hd66724/hd66725 can detect eight key inputs connected with strobe signal kst0, thus generating key scan interrupt (irq*). this means, the system can be activated from a completely inactive state. for details, refer to the key scan interrupt (wake-up function) section. turn off the lcd power supply: amp = 0 set standby mode: stb = 1 issue the start-oscillator instruction wait at least 10 ms cancel standby mode: stb = 0 turn on the lcd drive power supply: amp = 1 standby mode (key scan interrupt enabled) figure 58 procedure for setting and canceling standby mode
hd66724/hd66725 100 absolute maximum ratings * item symbol unit value notes* power supply voltage (1) v cc v ?.3 to +7.0 1 power supply voltage (2) v lcd ?gnd v ?.3 to +7.0 1, 2 input voltage vt v ?.3 to v cc + 0.3 1 operating temperature topr c ?0 to +85 storage temperature tstg c ?5 to +110 4 note: if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristics limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability.
hd66724/hd66725 101 dc characteristics (v cc = 1.8 to 5.5 v, ta = ?0 to +85 c* 3 ) item symbol min typ max unit test condition notes input high voltage v ih 0.7 v cc ? cc v 5, 6 input low voltage v il ?.3 0.15 v cc vv cc = 1.8 to 2.7 v 5, 6 input low voltage v il ?.3 0.15 v cc vv cc = 2.7 to 5.5 v 5, 6 output high voltage (1) (sda, db0-7 pins) v oh1 0.75 v cc vi oh = ?.1 ma 5, 7 output low voltage (1) (sda,db0-7 pins) v ol1 0.2 v cc vv cc = 1.8 to 2.7 v, i ol = 0.1 ma 5 output low voltage (1) (sda,db0-7 pins) v ol1 0.15 v cc vv cc = 2.7 to 5.5 v, i ol = 0.1 ma 5 output high voltage (2) (kst0-7, irq* pins) v oh2 0.7 v cc vi oh = 0.5 m a, v cc = 3 v 5 output low voltage (2) (kst0-7, irq* pins) v ol2 0.2 v cc vi ol = 0.1 ma 5 output high voltage (3) (port0-2 pins) v oh3 0.75 v cc v-i oh = 0.1ma 5 output low voltage (3) (port0-2 pins) v ol3 0.2 v cc vi ol = 0.1ma 5 driver on resistance (com pins) r com 3 20 k w id = 0.05 ma, v lcd = 5 v 8 driver on resistance (seg pins) r seg 3 30 k w id = 0.05 ma, v lcd = 5 v 8 i/o leakage current i li ? 1 m a vin = 0 to v cc 9 pull-up mos current (kin0-7, db0-7, sda pins) -i p 11040 m av cc = 3 v, vin = 0 v 5 current consumption during normal operation (v cc ?nd) i op ?035 m a r-c oscillation, v cc = 3 v, f osc = 32 khz (1/26 duty) 10, 11 current consumption during sleep mode (v cc ?nd) i sl ?1 m a r-c oscillation, v cc = 3 v, f osc = 32 khz (1/26 duty) 10, 11 current consumption during standby mode (v cc ?nd) i st 0.1 5 m a no r-c oscillation, v cc = 3 v, ta = 25 c 10, 11 lcd drive power supply current (v lcd ?nd) i ee ?735 m av lcd ?gnd = 5.5 v, f osc = 32 khz 11 lcd drive voltage (v lcd ?gnd) v lcd 3.0 6.5 v 12 note: for the numbered notes, refer to the electrical characteristics notes section following these tables.
hd66724/hd66725 102 booster characteristics item symbol min typ max unit test condition notes double-boost output voltage (vlout pin) v up2 5.5 5.9 v v cc = vci = 3.0 v, i o = 0.03 ma, c = 1 m f, f osc = 32 khz, ta = 25 c 15 triple-boost output voltage (vlout pin) v up3 6.1 6.5 v v cc = vci = 2.2 v, i o = 0.03 ma, c = 1 m f, f osc = 32 khz, ta = 25 c 15 maximum boost output voltage v up2 v up3 v cc 6.5 v 15 note: for the numbered notes, refer to the electrical characteristics notes section following these tables. ac characteristics (v cc = 1.8 to 5.5 v, ta = ?0 to +85 c* 3 ) clock characteristics (v cc = 1.8 to 5.5 v) item symbol min typ max unit test condition notes external clock frequency fcp 15 32 100 khz 13 external clock duty ratio duty 45 50 55 % 13 external clock rise time trcp 0.2 m s13 external clock fall time tfcp 0.2 m s13 cr oscillation frequency with external rf f osc1 25 32 40 rf = 620 k w , v cc = 3 v 14 cr oscillation frequency with internal rf f osc2 19 32 45 r1-osc2: short circuited v cc = 3 v note: for the numbered notes, refer to the electrical characteristics notes section following these tables.
hd66724/hd66725 103 68-system bus interface timing characteristics (vcc = 1.8 to 2.7 v) item symbol min typ max unit test condition enable cycle time write t cyce 800 ns figure 65 read 1200 enable high-level pulse width write pw eh 150 ns figure 65 read 450 enable low-level pulse width write pw el 300 ns figure 65 read 450 enable rise/fall time t er , t ef 25 ns figure 65 setup time (rs, r/w, to e, cs*) t ase 60 ns figure 65 address hold time t ahe 20 ns figure 65 write data set-up time t dswe 60 ns figure 65 write data hold time t he 20 ns figure 65 read data delay time t ddre 400 ns figure 65 read data hold time t dhre 5 ns figure 65 (vcc = 2.7 to 5.5 v) item symbol min typ max unit test condition enable cycle time write t cyce 500 ns figure 65 read 700 enable high-level pulse width write pw eh 80 ns figure 65 read 300 enable low-level pulse width write pw el 250 ns figure 65 read 300 enable rise/fall time t er , t ef 25 ns figure 65 setup time (rs, r/w, to e, cs*) t ase 60 ns figure 65 address hold time t ahe 20 ns figure 65 write data set-up time t dswe 60 ns figure 65 write data hold time t he 20 ns figure 65 read data delay time t ddre 250 ns figure 65 read data hold time t dhre 5 ns figure 65
hd66724/hd66725 104 80-system bus interface timing characteristics (vcc = 1.8 to 2.7 v) item symbol min typ max unit test condition bus cycle time write t cycw 800 ns figure 66 read t cycr 1200 ns figure 66 write low-level pulse width pw lw 150 ns figure 66 read low-level pulse width pw lr 450 ns figure 66 write high-level pulse width pw hw 300 ns figure 66 read high-level pulse width pw hr 450 ns figure 66 write/read rise/fall time t wrr , wrf 25 ns figure 66 setup time (rs to cs*, wr*, rd*) t as 60 ns figure 66 address hold time t ah 20 ns figure 66 write data set-up time t dsw 60 ns figure 66 write data hold time t h 20 ns figure 66 read data delay time t ddr 400 ns figure 66 read data hold time t dhr 5 ns figure 66 (vcc = 2.7 to 5.5 v) item symbol min typ max unit test condition bus cycle time write t cycw 500 ns figure 66 read t cycr 700 ns figure 66 write low-level pulse width pw lw 80 ns figure 66 read low-level pulse width pw lr 300 ns figure 66 write high-level pulse width pw hw 250 ns figure 66 read high-level pulse width pw hr 300 ns figure 66 write/read rise/fall time t wrr, wrf 25 ns figure 66 setup time (rs to cs*, wr*, rd*) t as 60 ns figure 66 address hold time t ah 20 ns figure 66 write data set-up time t dsw 60 ns figure 66 write data hold time t h 20 ns figure 66 read data delay time t ddr 250 ns figure 66 read data hold time t dhr 5 ns figure 66
hd66724/hd66725 105 clock-synchronized serial interface timing characteristics (v cc = 1.8 to 5.5 v) (v cc = 1.8 to 2.7 v) item symbol min typ max unit test condition serial clock cycle time write t scyc 0.5 20 m s figure 67 read t scyc 120 m s figure 67 serial clock high-level width write t sch 230 ns figure 67 read t sch 480 ns figure 67 serial clock low-level width write t scl 230 ns figure 67 read t scl 480 ns figure 67 serial clock rise/fall time t scf , t scr 20 ns figure 67 chip select set-up time t csu 60 ns figure 67 chip select hold time t ch 200 ns figure 67 serial input data set-up time t sisu 100 ns figure 67 serial input data hold time t sih 100 ns figure 67 serial output data delay time t sod 400 ns figure 67 serial output hold time t soh 5 ns figure 67 (v cc = 2.7 to 5.5 v) item symbol min typ max unit test condition serial clock cycle time write t scyc 0.2 20 m s figure 67 read t scyc 0.5 20 m s figure 67 serial clock high-level width write t sch 80 ns figure 67 read t sch 230 ns figure 67 serial clock low-level width write t scl 80 ns figure 67 read t scl 230 ns figure 67 serial clock rise/fall time t scf , t scr 20 ns figure 67 chip select setup time t csu 60 ns figure 67 chip select hold time t ch 200 ns figure 67 serial input data set-up time t sisu 40 ns figure 67 serial input data hold time t sih 40 ns figure 67 serial output data delay time t sod 200 ns figure 67 serial output hold time t soh 5 ns figure 67
hd66724/hd66725 106 reset timing characteristics (v cc = 1.8 to 5.5 v) item symbol min typ max unit test condition reset low-level width t res 1 ms figure 68
hd66724/hd66725 107 electrical characteristics notes 1. all voltage values are referred to gnd = 0 v. if the lsi is used above the absolute maximum ratings, it may become permanently damaged. using the lsi within the given electrical characteristic is strongly recommended to ensure normal operation. if these electrical characteristics are exceeded, the lsi may malfunction or exhibit poor reliability. 2. vlcd > gnd must be maintained. 3. for bare die products, specified at 85?c. 4. for bare die products, specified by the common die shipment specification. 5. the following three circuits are i/o pin configurations (figure 59). pins: reset*, cs*, e/wr*/scl, rs, osc1, opoff, im2/1, im0/id, test pins: kst3 to kst0, irq* port2 to port0, osc2 pmos nmos vcc gnd pin: rw/rd*/sda pmos nmos vcc gnd (tri-state output circuit) (input circuit) (pull-up mos) pmos pmos nmos pmos nmos gnd vcc output enable output data vcc vcc im1 im2 figure 59 i/o pin configuration
hd66724/hd66725 108 im0 pin: db7/kin7 to db4/kin4 (tri-state output circuit) (input circuit) (pull-up mos) pmos pmos nmos pmos nmos gnd vcc output enable output data vcc vcc im1 pin: db3/kin3 to db0/kin0 (tri-state output circuit) (input circuit) (pull-up mos) pmos pmos nmos pmos nmos gnd vcc output enable output data vcc vcc im1 figure 59 i/o pin configuration (cont) 6. the test pin must be grounded and the im2/1, im0/id, and opoff pins must be grounded or connected to vcc. 7. corresponds to the high output for clock-synchronized serial interface. 8. applies to the resistor value (rcom) between power supply pins v1out, v2out, v5out, gnd and common signal pins (com1 to com24, coms1 and coms2), and resistor value (rseg) between power supply pins v1out, v3out, v4out, gnd and segment signal pins (seg1 to seg72 (96)), when current id is flown through all driver output pins. 9. this excludes the current flowing through pull-up moss and output drive moss. 10. this excludes the current flowing through the input/output units. the input level must be fixed high or low because through current increases if the cmos input is left floating. 11. the following shows the relationship between the operation frequency (fosc) and current consumption (icc) (figure 60).
hd66724/hd66725 109 cr oscillation frequency: fosc (khz) 30 20 10 0 iop ( a) vcc = 3 v 0 1020304050 display on (typ.) sleep (typ.) 30 20 10 0 i lcd ( a) vcc = 3 v, fosc = 32 khz 3.0 lcd drive voltage: vlcd (v) 4.0 5.0 6.0 standby (typ.) typ. figure 60 relationship between the operation frequency and current consumption 12. each com and seg output voltage is within 0.15 v of the lcd voltage (vcc, v1, v2, v3, v4, v5) when there is no load. 13. applies to the external clock input (figure 61). oscillator osc1 open osc2 t rcp t fcp th tl 0.7vcc 0.5vcc 0.3vcc duty = th+tl th 100% figure 61 external clock supply
hd66724/hd66725 110 14. applies to the internal oscillator operations using oscillation resistor rf (figure 62). osc1 osc2 rf since the oscillation frequency varies depending on the osc1 and osc2 pin capacitance, the wiring length to these pins should be minimized. external resistance (rf) cr oscillation frequency : fosc vcc = 1.8 v 40 khz 33 khz 30 khz 28 khz 26 khz 24 khz vcc = 2.2 v 45 khz 36 khz 33 khz 30 khz 29 khz 27 khz vcc = 3.0 v 48 khz 38 khz 35 khz 32 khz 30 khz 28 khz vcc = 4.0 v 50 khz 40 khz 36 khz 33 khz 31 khz 29 khz vcc = 5.0 v 51 khz 41 khz 37 khz 33 khz 31 khz 29 khz 390 k 510 k 560 k 620 k 680 k 750 k figure 62 internal oscillation 15. booster characteristics test circuits are shown in figure 63. (triple boosting) (double boosting) 1 f 1 f 1 f 1 f 1 f gnd vcc vci c1+ c1- vlout + v lcd c2+ c2- + gnd vcc vci c1+ c1- vlout + v lcd c2+ c2- + + figure 63 booster
hd66724/hd66725 111 vup2 = vlcd ?gnd; vup3 = vlcd ?gnd (i) relation between the obtained voltage and input voltage vci (v) vci = vcc, fosc = 32 khz, ta = 25?c (ii) relation between the obtained voltage and temperature vci = vcc, fosc = 32 khz, ta = 25?c referential data 3.0 2.5 2.0 1.5 3.0 4.0 5.0 6.0 typ. 2.5 2.0 1.5 1.0 3.0 4.0 5.0 6.0 7.0 typ. double boosting triple boosting vci (v) vup2 (v) vup3 (v) 100 60 20 0 -20 -60 5.0 5.5 6.0 6.5 100 60 20 0 -20 -60 6.0 6.5 7.0 double boosting triple boosting vup2 (v) vup3 (v) ta ( c) ta ( c) vci = vcc = 3.0 v, fosc = 32 khz, io = 30 a vci = vcc = 2.2 v, fosc = 32 khz, io = 30 a typ. typ. figure 63 booster (cont)
hd66724/hd66725 112 (iv) relation between the obtained voltage and current (iii) relation between the obtained voltage and capacitance vci = vcc = 3.0 v, fosc = 32 khz, io = 30 a vci = vcc = 2.2 v, fosc = 32 khz, io = 30 a 1.5 1.0 0.5 4.0 5.5 6.0 6.5 7.0 c ( f) vup3(v) double boosting triple boosting c ( f) vup2(v) 1.5 1.0 0.5 4.5 5.0 5.5 6.0 6.5 200 150 100 50 0 4.5 5.0 5.5 6.0 6.5 7.0 typ. 200 150 100 50 0 5.0 5.5 6.0 6.5 7.0 typ. typ. typ. double boosting triple boosting io ( a) io ( a) vci = vcc = 3.0 v, fosc = 32 khz, ta = 25 c vci = vcc = 2.2 v, fosc = 32 khz, ta = 25 c vup3(v) vup2(v) figure 63 booster (cont)
hd66724/hd66725 113 load circuits ac characteristics test load circuits data bus: db7 to db0, sda test point 50 pf figure 64 load circuit
hd66724/hd66725 114 timing characteristics 68-system bus operation rs r/w cs* e db0 to db7 db0 to db7 v ih v il t ase t ahe pw eh t ef t er t dswe t he t ddre t dhre v note: pw eh is defined as the overlapped period of the low of cs* and the high of e. oh1 v ol1 v oh1 v ol1 v ih v il v ih v il v ih v il v il v ih v il v ih v il pw el write data read data t cyce figure 65 68-system bus timing
hd66724/hd66725 115 80-system bus operation rs cs* wr* rd* db0 to db7 db0 to db7 v ih v il t as t ah pw lr, pw ld t wrf t wrr t dsw t hwr t cycw, t cycr t ddr t dhrd v note: pw lw and pw lr is defined as the overlapped period of the low of cs* and the low of wr * /rd * . oh1 v ol1 v oh1 v ol1 v ih v il v ih v il v ih v il v ih v il v ih v il v ih pw hr, pw hd write data read data figure 66 80-system bus timing clock-synchronized serial operation cs* start: s end: p scl sda t csu t sch v il t sisu tscr v ih v il v ih v il v ih v il t ch v ih v il v ih v il t cwl tscf t sih v il t scyc v ih sda t sod v oh1 v oh1 v oh1 v ol1 t soh v il input data output data output data input data figure 67 clock-synchronized serial interface timing
hd66724/hd66725 116 reset operation reset* vil vil t res figure 68 reset timing
hd66724/hd66725 117 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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